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Tests: Add param type to t_typename test
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@ -257,6 +257,7 @@ class LinkCellsVisitor final : public VNVisitor {
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// For historical reasons virtual interface reference variables remain VARs
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if (m_varp && !nodep->isVirtual()) m_varp->setIfaceRef();
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// Note cannot do modport resolution here; modports are allowed underneath generates
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UINFO(4, "Link IfaceRef done: " << nodep << endl);
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}
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void visit(AstPackageExport* nodep) override {
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@ -502,10 +503,10 @@ class LinkCellsVisitor final : public VNVisitor {
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AstIfaceRefDType* const idtypep = new AstIfaceRefDType{
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nodep->fileline(), nodep->name(), nodep->modp()->name()};
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idtypep->ifacep(nullptr); // cellp overrides
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// In the case of arrayed interfaces, we replace cellp when de-arraying in V3Inst
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idtypep->cellp(nodep); // Only set when real parent cell known.
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AstVar* varp;
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if (nodep->rangep()) {
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// For arrayed interfaces, we replace cellp when de-arraying in V3Inst
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AstNodeArrayDType* const arrp
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= new AstUnpackArrayDType{nodep->fileline(), VFlagChildDType{}, idtypep,
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nodep->rangep()->cloneTree(true)};
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@ -2745,7 +2745,7 @@ if __name__ == '__main__':
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parser.add_argument('--fail-max',
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action='store',
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default=None,
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help='run Verilator executable with gdb')
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help='after specified number of failures, skip remaining tests')
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parser.add_argument('--gdb', action='store_true', help='run Verilator executable with gdb')
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parser.add_argument('--gdbbt',
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action='store_true',
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@ -14,6 +14,7 @@
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"bit[2:0]" ==? "bit[2:0]"
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"int" ==? "int"
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"bit[9:1]" ==? "bit[9:1]"
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"bit[9:1]" ==? "bit[9:1]"
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"string$[longint]" ==? "string$[longint]"
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"int$[$]" ==? "int$[$]"
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"int$[$:3]" ==? "int$[$:3]"
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@ -15,7 +15,8 @@ int signed Y; // "int"
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package A;
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enum {A,B,C=99} X; // "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1"
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typedef bit [9:1'b1] word; // "A::bit[9:1]"
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typedef bit [9:1'b1] word_t; // "A::bit[9:1]"
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localparam type WORD_T = word_t;
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endpackage : A
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import A::*;
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@ -31,6 +32,7 @@ module t(/*AUTOARG*/);
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real r;
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logic l;
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typedef bit mybit_t;
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localparam type MYBIT_T = mybit_t;
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mybit_t [2:0] bitp20;
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mybit_t bitu32 [3:2];
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mybit_t bitu31 [3:1][4:5];
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@ -69,7 +71,8 @@ module t(/*AUTOARG*/);
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`printtype(X, "bit[2:0]");
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`printtype(Y, "int");
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`printtype(A::word, "bit[9:1]");
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`printtype(A::word_t, "bit[9:1]");
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`printtype(A::WORD_T, "bit[9:1]");
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`printtype(assoc, "string$[longint]");
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`printtype(q, "int$[$]");
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`printtype(q3, "int$[$:3]"); // Some omit :3 - need it so != unbounded
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