diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index 718541db7..c25ed16f3 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -257,6 +257,7 @@ class LinkCellsVisitor final : public VNVisitor {
         // For historical reasons virtual interface reference variables remain VARs
         if (m_varp && !nodep->isVirtual()) m_varp->setIfaceRef();
         // Note cannot do modport resolution here; modports are allowed underneath generates
+        UINFO(4, "Link IfaceRef done: " << nodep << endl);
     }
 
     void visit(AstPackageExport* nodep) override {
@@ -502,10 +503,10 @@ class LinkCellsVisitor final : public VNVisitor {
                 AstIfaceRefDType* const idtypep = new AstIfaceRefDType{
                     nodep->fileline(), nodep->name(), nodep->modp()->name()};
                 idtypep->ifacep(nullptr);  // cellp overrides
-                // In the case of arrayed interfaces, we replace cellp when de-arraying in V3Inst
                 idtypep->cellp(nodep);  // Only set when real parent cell known.
                 AstVar* varp;
                 if (nodep->rangep()) {
+                    // For arrayed interfaces, we replace cellp when de-arraying in V3Inst
                     AstNodeArrayDType* const arrp
                         = new AstUnpackArrayDType{nodep->fileline(), VFlagChildDType{}, idtypep,
                                                   nodep->rangep()->cloneTree(true)};
diff --git a/test_regress/driver.py b/test_regress/driver.py
index 75ded4d44..0e3849280 100755
--- a/test_regress/driver.py
+++ b/test_regress/driver.py
@@ -2745,7 +2745,7 @@ if __name__ == '__main__':
     parser.add_argument('--fail-max',
                         action='store',
                         default=None,
-                        help='run Verilator executable with gdb')
+                        help='after specified number of failures, skip remaining tests')
     parser.add_argument('--gdb', action='store_true', help='run Verilator executable with gdb')
     parser.add_argument('--gdbbt',
                         action='store_true',
diff --git a/test_regress/t/t_typename.out b/test_regress/t/t_typename.out
index b95d23411..133f56582 100644
--- a/test_regress/t/t_typename.out
+++ b/test_regress/t/t_typename.out
@@ -14,6 +14,7 @@
 "bit[2:0]" ==? "bit[2:0]"
 "int" ==? "int"
 "bit[9:1]" ==? "bit[9:1]"
+"bit[9:1]" ==? "bit[9:1]"
 "string$[longint]" ==? "string$[longint]"
 "int$[$]" ==? "int$[$]"
 "int$[$:3]" ==? "int$[$:3]"
diff --git a/test_regress/t/t_typename.v b/test_regress/t/t_typename.v
index 624da2576..ea6c2d088 100644
--- a/test_regress/t/t_typename.v
+++ b/test_regress/t/t_typename.v
@@ -15,7 +15,8 @@ int signed Y; // "int"
 
 package A;
    enum {A,B,C=99} X; // "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1"
-   typedef bit [9:1'b1] word; // "A::bit[9:1]"
+   typedef bit [9:1'b1] word_t; // "A::bit[9:1]"
+   localparam type WORD_T = word_t;
 endpackage : A
 
 import A::*;
@@ -31,6 +32,7 @@ module t(/*AUTOARG*/);
    real r;
    logic l;
    typedef bit mybit_t;
+   localparam type MYBIT_T = mybit_t;
    mybit_t [2:0] bitp20;
    mybit_t bitu32 [3:2];
    mybit_t bitu31 [3:1][4:5];
@@ -69,7 +71,8 @@ module t(/*AUTOARG*/);
       `printtype(X, "bit[2:0]");
       `printtype(Y, "int");
 
-      `printtype(A::word, "bit[9:1]");
+      `printtype(A::word_t, "bit[9:1]");
+      `printtype(A::WORD_T, "bit[9:1]");
       `printtype(assoc, "string$[longint]");
       `printtype(q, "int$[$]");
       `printtype(q3, "int$[$:3]");  // Some omit :3 - need it so != unbounded