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Fix float parameters without parens

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This commit is contained in:
Wilson Snyder 2022-11-21 06:48:13 -05:00
parent 62bdd3ab49
commit d3c1f4353e
2 changed files with 16 additions and 8 deletions
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15
src/verilog.y
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@ -1322,12 +1322,11 @@ parameter_value_assignmentE<pinp>: // IEEE: [ parameter_value_assignment ]
parameter_value_assignment<pinp>: // IEEE: parameter_value_assignment
'#' '(' cellparamList ')' { $$ = $3; }
// // Parentheses are optional around a single parameter
| '#' yaINTNUM { $$ = new AstPin($<fl>2, 1, "", new AstConst($<fl>2, *$2)); }
| '#' yaFLOATNUM { $$ = new AstPin($<fl>2, 1, "",
new AstConst($<fl>2, AstConst::Unsized32(),
(int)(($2<0)?($2-0.5):($2+0.5)))); }
| '#' timeNumAdjusted { $$ = new AstPin($<fl>2, 1, "", $2); }
| '#' idClassSel { $$ = new AstPin($<fl>2, 1, "", $2); }
| '#' yaINTNUM { $$ = new AstPin{$<fl>2, 1, "", new AstConst{$<fl>2, *$2}}; }
| '#' yaFLOATNUM { $$ = new AstPin{$<fl>2, 1, "",
new AstConst{$<fl>2, AstConst::RealDouble{}, $2}}; }
| '#' timeNumAdjusted { $$ = new AstPin{$<fl>2, 1, "", $2}; }
| '#' idClassSel { $$ = new AstPin{$<fl>2, 1, "", $2}; }
// // Not needed in Verilator:
// // Side effect of combining *_instantiations
// // '#' delay_value { UNSUP }
@ -2794,8 +2793,8 @@ delay_control<delayp>: //== IEEE: delay_control
delay_value<nodeExprp>: // ==IEEE:delay_value
// // IEEE: ps_identifier
packageClassScopeE varRefBase { $$ = AstDot::newIfPkg($<fl>2, $1, $2); }
| yaINTNUM { $$ = new AstConst($<fl>1, *$1); }
| yaFLOATNUM { $$ = new AstConst($<fl>1, AstConst::RealDouble(), $1); }
| yaINTNUM { $$ = new AstConst{$<fl>1, *$1}; }
| yaFLOATNUM { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
| timeNumAdjusted { $$ = $1; }
;

9
test_regress/t/t_param.v
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@ -13,6 +13,7 @@ module t (/*AUTOARG*/
m1 #(PAR) m1();
m3 #(PAR) m3();
mnooverride #(10) mno();
mreal #1.2 mr();
input clk;
integer cyc=1;
@ -74,3 +75,11 @@ module mnooverride;
if (PAR !== 10) $stop;
end
endmodule
module mreal;
parameter real REAL = 99.99;
initial begin
$display("%f", REAL);
if (REAL !== 1.2) $stop;
end
endmodule