From d3c1f4353e5136f3d830e2775d8e3c1697d9f044 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 21 Nov 2022 06:48:13 -0500 Subject: [PATCH] Fix float parameters without parens --- src/verilog.y | 15 +++++++-------- test_regress/t/t_param.v | 9 +++++++++ 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/verilog.y b/src/verilog.y index f46cc147b..d7c64917b 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1322,12 +1322,11 @@ parameter_value_assignmentE: // IEEE: [ parameter_value_assignment ] parameter_value_assignment: // IEEE: parameter_value_assignment '#' '(' cellparamList ')' { $$ = $3; } // // Parentheses are optional around a single parameter - | '#' yaINTNUM { $$ = new AstPin($2, 1, "", new AstConst($2, *$2)); } - | '#' yaFLOATNUM { $$ = new AstPin($2, 1, "", - new AstConst($2, AstConst::Unsized32(), - (int)(($2<0)?($2-0.5):($2+0.5)))); } - | '#' timeNumAdjusted { $$ = new AstPin($2, 1, "", $2); } - | '#' idClassSel { $$ = new AstPin($2, 1, "", $2); } + | '#' yaINTNUM { $$ = new AstPin{$2, 1, "", new AstConst{$2, *$2}}; } + | '#' yaFLOATNUM { $$ = new AstPin{$2, 1, "", + new AstConst{$2, AstConst::RealDouble{}, $2}}; } + | '#' timeNumAdjusted { $$ = new AstPin{$2, 1, "", $2}; } + | '#' idClassSel { $$ = new AstPin{$2, 1, "", $2}; } // // Not needed in Verilator: // // Side effect of combining *_instantiations // // '#' delay_value { UNSUP } @@ -2794,8 +2793,8 @@ delay_control: //== IEEE: delay_control delay_value: // ==IEEE:delay_value // // IEEE: ps_identifier packageClassScopeE varRefBase { $$ = AstDot::newIfPkg($2, $1, $2); } - | yaINTNUM { $$ = new AstConst($1, *$1); } - | yaFLOATNUM { $$ = new AstConst($1, AstConst::RealDouble(), $1); } + | yaINTNUM { $$ = new AstConst{$1, *$1}; } + | yaFLOATNUM { $$ = new AstConst{$1, AstConst::RealDouble{}, $1}; } | timeNumAdjusted { $$ = $1; } ; diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index 884b8f23c..abcc6e402 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -13,6 +13,7 @@ module t (/*AUTOARG*/ m1 #(PAR) m1(); m3 #(PAR) m3(); mnooverride #(10) mno(); + mreal #1.2 mr(); input clk; integer cyc=1; @@ -74,3 +75,11 @@ module mnooverride; if (PAR !== 10) $stop; end endmodule + +module mreal; + parameter real REAL = 99.99; + initial begin + $display("%f", REAL); + if (REAL !== 1.2) $stop; + end +endmodule