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Suppress WIDTH warnings when adding/subtracting 1'b1.

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This commit is contained in:
Wilson Snyder 2010-12-02 14:00:43 -05:00
parent 48047d523a
commit cfd07ccd34
4 changed files with 41 additions and 0 deletions
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2
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add -F option to read relative option files, bug297. [Neil Hamilton]
*** Suppress WIDTH warnings when adding/subtracting 1'b1.
* Verilator 3.805 2010/11/02
**** Add warning when directory contains spaces, msg378. [Salman Sheikh]

6
src/V3Width.cpp
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@ -1163,6 +1163,12 @@ void WidthVisitor::widthCheck (AstNode* nodep, const char* side,
// Maybe this should be a special warning? Not for now.
ignoreWarn = true;
}
if ((nodep->castAdd() && underp->width()==1 && underp->isOne())
|| (nodep->castSub() && underp->width()==1 && underp->isOne() && 0==strcmp(side,"RHS"))) {
// "foo + 1'b1", or "foo - 1'b1" are very common, people assume they extend correctly
ignoreWarn = true;
}
if (bad && !ignoreWarn) {
if (debug()>4) nodep->backp()->dumpTree(cout," back: ");
nodep->v3warn(WIDTH,"Operator "<<nodep->prettyTypeName()

18
test_regress/t/t_lint_width.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--lint-only"],
make_top_shell => 0,
make_main => 0,
verilator_make_gcc => 0,
) if $Self->{v3};
ok(1);
1;

15
test_regress/t/t_lint_width.v Normal file
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@ -0,0 +1,15 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t ();
// This isn't a width violation, as +/- 1'b1 is a common idiom
// that's fairly harmless
wire [4:0] five = 5'd5;
wire [4:0] suma = five + 1'b1;
wire [4:0] sumb = 1'b1 + five;
wire [4:0] sumc = five - 1'b1;
endmodule