diff --git a/Changes b/Changes
index 164c29498..2ee5efcda 100644
--- a/Changes
+++ b/Changes
@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add -F option to read relative option files, bug297. [Neil Hamilton]
 
+***  Suppress WIDTH warnings when adding/subtracting 1'b1.
+
 * Verilator 3.805 2010/11/02
 
 **** Add warning when directory contains spaces, msg378.  [Salman Sheikh]
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 2dfed3080..1a2ae9e7f 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1163,6 +1163,12 @@ void WidthVisitor::widthCheck (AstNode* nodep, const char* side,
 	// Maybe this should be a special warning?  Not for now.
 	ignoreWarn = true;
     }
+    if ((nodep->castAdd() && underp->width()==1 && underp->isOne())
+	|| (nodep->castSub() && underp->width()==1 && underp->isOne() && 0==strcmp(side,"RHS"))) {
+	// "foo + 1'b1", or "foo - 1'b1" are very common, people assume they extend correctly
+	ignoreWarn = true;
+    }
+	
     if (bad && !ignoreWarn) {
 	if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
 	nodep->v3warn(WIDTH,"Operator "<<nodep->prettyTypeName()
diff --git a/test_regress/t/t_lint_width.pl b/test_regress/t/t_lint_width.pl
new file mode 100755
index 000000000..7f5263655
--- /dev/null
+++ b/test_regress/t/t_lint_width.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 make_top_shell => 0,
+	 make_main => 0,
+	 verilator_make_gcc => 0,
+	 ) if $Self->{v3};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v
new file mode 100644
index 000000000..06635b68f
--- /dev/null
+++ b/test_regress/t/t_lint_width.v
@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t ();
+
+   // This isn't a width violation, as +/- 1'b1 is a common idiom
+   // that's fairly harmless
+   wire [4:0] five = 5'd5;
+   wire [4:0] suma = five + 1'b1;
+   wire [4:0] sumb = 1'b1 + five;
+   wire [4:0] sumc = five - 1'b1;
+
+endmodule