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Fix DfgToAst conversion of CountBits (#4101) (#4143)

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Geza Lore 2023-04-23 14:49:44 +02:00 committed by GitHub
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4 changed files with 30 additions and 2 deletions
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@ -41,6 +41,7 @@ Verilator 5.009 devel
* Fix interface generate begin (#4065). [Srinivasan Venkataramanan] * Fix interface generate begin (#4065). [Srinivasan Venkataramanan]
* Fix false error on new const assignment (#4098). [Tudor Timi] * Fix false error on new const assignment (#4098). [Tudor Timi]
* Fix unpacked structs under classes (#4102). [Tudor Timi] * Fix unpacked structs under classes (#4102). [Tudor Timi]
* Fix DFG error on $countbits (#4101). [Paul Donahue]
* Fix false ENUMVALUE on expressions and arrays. * Fix false ENUMVALUE on expressions and arrays.
* Fix unnecessary verilated_std.sv waivers in --waiver-output. * Fix unnecessary verilated_std.sv waivers in --waiver-output.

3
src/V3DfgDfgToAst.cpp
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@ -59,8 +59,7 @@ AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeExpr*>( //
const DfgCountOnes* vtxp, AstNodeExpr* op1) { const DfgCountOnes* vtxp, AstNodeExpr* op1) {
AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1}; AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1};
// Set dtype same as V3Width // Set dtype same as V3Width
const int selwidth = V3Number::log2b(nodep->lhsp()->width()) + 1; nodep->dtypeSetLogicSized(32, VSigning::UNSIGNED);
nodep->dtypeSetLogicSized(selwidth, VSigning::UNSIGNED);
return nodep; return nodep;
} }

16
test_regress/t/t_dfg_4104.pl Executable file
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@ -0,0 +1,16 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Geza Lore. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile();
ok(1);
1;

12
test_regress/t/t_dfg_4104.v Normal file
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@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module v(input logic t);
endmodule
module top(input logic [2:0] c);
v v1((int'(c) + int'($countones(c))) > 2);
endmodule