diff --git a/Changes b/Changes
index 75c95ee2f..8f4241c80 100644
--- a/Changes
+++ b/Changes
@@ -41,6 +41,7 @@ Verilator 5.009 devel
 * Fix interface generate begin (#4065). [Srinivasan Venkataramanan]
 * Fix false error on new const assignment (#4098). [Tudor Timi]
 * Fix unpacked structs under classes (#4102). [Tudor Timi]
+* Fix DFG error on $countbits (#4101). [Paul Donahue]
 * Fix false ENUMVALUE on expressions and arrays.
 * Fix unnecessary verilated_std.sv waivers in --waiver-output.
 
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index 3932162be..6667ee35f 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -59,8 +59,7 @@ AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeExpr*>(  //
     const DfgCountOnes* vtxp, AstNodeExpr* op1) {
     AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1};
     // Set dtype same as V3Width
-    const int selwidth = V3Number::log2b(nodep->lhsp()->width()) + 1;
-    nodep->dtypeSetLogicSized(selwidth, VSigning::UNSIGNED);
+    nodep->dtypeSetLogicSized(32, VSigning::UNSIGNED);
     return nodep;
 }
 
diff --git a/test_regress/t/t_dfg_4104.pl b/test_regress/t/t_dfg_4104.pl
new file mode 100755
index 000000000..4087b203c
--- /dev/null
+++ b/test_regress/t/t_dfg_4104.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dfg_4104.v b/test_regress/t/t_dfg_4104.v
new file mode 100644
index 000000000..508f93a57
--- /dev/null
+++ b/test_regress/t/t_dfg_4104.v
@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+module v(input logic t);
+endmodule
+
+module top(input logic [2:0] c);
+  v v1((int'(c) + int'($countones(c))) > 2);
+endmodule