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Show examples with timestamps as 64 bits

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This commit is contained in:
Wilson Snyder 2011-11-06 11:54:17 -05:00
parent 88a2b0b911
commit b4642d3fd4
3 changed files with 9 additions and 6 deletions
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7
bin/verilator
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@ -1308,10 +1308,13 @@ example:
Vtop *top; // Instantiation of module
unsigned int main_time = 0; // Current simulation time
vluint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
return main_time; // converts to double, to match
// what SystemC does
}
int main(int argc, char** argv) {

6
test_c/sim_main.cpp
View File

@ -13,10 +13,10 @@
Vtop *top; // Instantiation of module
unsigned int main_time = 0; // Current simulation time
vluint64_t main_time = 0; // Current simulation time (64-bit unsigned)
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
return main_time; // Note does conversion to real, to match SystemC
}
int main(int argc, char **argv, char **env) {
@ -59,7 +59,7 @@ int main(int argc, char **argv, char **env) {
#endif
// Read outputs
VL_PRINTF ("[%d] %x %x %x %x %x_%08x_%08x\n",
VL_PRINTF ("[%" VL_PRI64 "d] %x %x %x %x %x_%08x_%08x\n",
main_time, top->clk, top->reset_l, top->passed,
top->out_small, top->out_wide[2], top->out_wide[1], top->out_wide[0]);

2
test_verilated/sim_main.cpp
View File

@ -12,7 +12,7 @@
Vvgen *top;
unsigned int main_time = 0;
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;