From b4642d3fd47d5dc6005f30c21d36984128adc5b1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 6 Nov 2011 11:54:17 -0500
Subject: [PATCH] Show examples with timestamps as 64 bits

---
 bin/verilator               | 7 +++++--
 test_c/sim_main.cpp         | 6 +++---
 test_verilated/sim_main.cpp | 2 +-
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/bin/verilator b/bin/verilator
index cc2ccde45..ec38cd6f0 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1308,10 +1308,13 @@ example:
 
 	Vtop *top;			// Instantiation of module
 
-	unsigned int main_time = 0;	// Current simulation time
+	vluint64_t main_time = 0;	// Current simulation time
+	// This is a 64-bit integer to reduce wrap over issues and
+	// allow modulus.  You can also use a double, if you wish.
 
 	double sc_time_stamp () {	// Called by $time in Verilog
-	    return main_time;
+	    return main_time;		// converts to double, to match
+					// what SystemC does    
 	}
 
 	int main(int argc, char** argv) {
diff --git a/test_c/sim_main.cpp b/test_c/sim_main.cpp
index 5a7a6a6db..5c06f12ba 100644
--- a/test_c/sim_main.cpp
+++ b/test_c/sim_main.cpp
@@ -13,10 +13,10 @@
 
 Vtop *top;			// Instantiation of module
 
-unsigned int main_time = 0;	// Current simulation time
+vluint64_t main_time = 0;	// Current simulation time (64-bit unsigned)
 
 double sc_time_stamp () {	// Called by $time in Verilog
-    return main_time;
+    return main_time;		// Note does conversion to real, to match SystemC
 }
 
 int main(int argc, char **argv, char **env) {
@@ -59,7 +59,7 @@ int main(int argc, char **argv, char **env) {
 #endif
 
 	// Read outputs
-	VL_PRINTF ("[%d] %x %x %x %x %x_%08x_%08x\n",
+	VL_PRINTF ("[%" VL_PRI64 "d] %x %x %x %x %x_%08x_%08x\n",
 		   main_time, top->clk, top->reset_l, top->passed,
 		   top->out_small, top->out_wide[2], top->out_wide[1], top->out_wide[0]);
 
diff --git a/test_verilated/sim_main.cpp b/test_verilated/sim_main.cpp
index 380849e63..97247b9c7 100644
--- a/test_verilated/sim_main.cpp
+++ b/test_verilated/sim_main.cpp
@@ -12,7 +12,7 @@
 
 Vvgen *top;
 
-unsigned int main_time = 0;
+vluint64_t main_time = 0;
 
 double sc_time_stamp () {
     return main_time;