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Fix output with tri1, but489

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This commit is contained in:
Wilson Snyder 2012-04-24 07:12:51 -04:00
parent ffbd595d88
commit b1507060ad
3 changed files with 25 additions and 4 deletions
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5
src/V3Ast.h
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@ -387,6 +387,11 @@ public:
"PORT", "PORT",
"BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"}; "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"};
return names[m_e]; } return names[m_e]; }
bool isSignal() const { return (m_e==WIRE || m_e==IMPLICITWIRE
|| m_e==TRIWIRE
|| m_e==TRI0 || m_e==TRI1
|| m_e==SUPPLY0 || m_e==SUPPLY1
|| m_e==VAR); }
}; };
inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); } inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); }
inline bool operator== (AstVarType lhs, AstVarType::en rhs) { return (lhs.m_e == rhs); } inline bool operator== (AstVarType lhs, AstVarType::en rhs) { return (lhs.m_e == rhs); }

3
src/V3AstNodes.h
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@ -757,8 +757,7 @@ public:
bool isPrimaryIO() const { return m_primaryIO; } bool isPrimaryIO() const { return m_primaryIO; }
bool isPrimaryIn() const { return isPrimaryIO() && isInput(); } bool isPrimaryIn() const { return isPrimaryIO() && isInput(); }
bool isIO() const { return (m_input||m_output); } bool isIO() const { return (m_input||m_output); }
bool isSignal() const { return (varType()==AstVarType::WIRE || varType()==AstVarType::IMPLICITWIRE bool isSignal() const { return varType().isSignal(); }
|| varType()==AstVarType::VAR); }
bool isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP bool isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP
|| varType()==AstVarType::STMTTEMP || varType()==AstVarType::XTEMP); } || varType()==AstVarType::STMTTEMP || varType()==AstVarType::XTEMP); }
bool isToggleCoverable() const { return ((isIO() || isSignal()) bool isToggleCoverable() const { return ((isIO() || isSignal())

21
test_regress/t/t_tri_pull01.v
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@ -26,7 +26,11 @@ module t (/*AUTOARG*/
bufif1 (t1, crc[1], cyc[1:0]==2'b00); bufif1 (t1, crc[1], cyc[1:0]==2'b00);
bufif1 (t1, crc[2], cyc[1:0]==2'b10); bufif1 (t1, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {59'h0, t1, 3'h0, t0}; tri t2;
t_tri t_tri (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t2, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {55'h0, t2, 3'h0, t1, 3'h0, t0};
// Test loop // Test loop
always @ (posedge clk) begin always @ (posedge clk) begin
@ -50,7 +54,7 @@ module t (/*AUTOARG*/
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop; if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match) // What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h14f90df4eab2c499 `define EXPECTED_SUM 64'hfb06f31a3805822e
if (sum !== `EXPECTED_SUM) $stop; if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
@ -58,3 +62,16 @@ module t (/*AUTOARG*/
end end
endmodule endmodule
module t_tri (/*AUTOARG*/
// Outputs
t2,
// Inputs
d, oe
);
output t2;
input d;
input oe;
tri1 t2;
bufif1 (t2, d, oe);
endmodule