diff --git a/src/V3Ast.h b/src/V3Ast.h
index 226da8e35..b83304e2a 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -387,6 +387,11 @@ public:
 	    "PORT",
 	    "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"};
 	return names[m_e]; }
+    bool isSignal() const  { return (m_e==WIRE || m_e==IMPLICITWIRE
+				     || m_e==TRIWIRE
+				     || m_e==TRI0 || m_e==TRI1
+				     || m_e==SUPPLY0 || m_e==SUPPLY1
+				     || m_e==VAR); }
   };
   inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); }
   inline bool operator== (AstVarType lhs, AstVarType::en rhs) { return (lhs.m_e == rhs); }
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 8b1f08975..d00a31ceb 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -757,8 +757,7 @@ public:
     bool	isPrimaryIO() const { return m_primaryIO; }
     bool	isPrimaryIn() const { return isPrimaryIO() && isInput(); }
     bool	isIO() const  { return (m_input||m_output); }
-    bool	isSignal() const  { return (varType()==AstVarType::WIRE || varType()==AstVarType::IMPLICITWIRE
-					    || varType()==AstVarType::VAR); }
+    bool	isSignal() const  { return varType().isSignal(); }
     bool	isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP
 					 || varType()==AstVarType::STMTTEMP || varType()==AstVarType::XTEMP); }
     bool	isToggleCoverable() const  { return ((isIO() || isSignal())
diff --git a/test_regress/t/t_tri_pull01.v b/test_regress/t/t_tri_pull01.v
index 3cb41ab01..24a8ae634 100644
--- a/test_regress/t/t_tri_pull01.v
+++ b/test_regress/t/t_tri_pull01.v
@@ -26,7 +26,11 @@ module t (/*AUTOARG*/
    bufif1 (t1, crc[1], cyc[1:0]==2'b00);
    bufif1 (t1, crc[2], cyc[1:0]==2'b10);
 
-   wire [63:0] 	result = {59'h0, t1, 3'h0, t0};
+   tri 	t2;
+   t_tri t_tri (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
+   bufif1 (t2, crc[2], cyc[1:0]==2'b10);
+
+   wire [63:0] 	result = {55'h0, t2, 3'h0, t1, 3'h0, t0};
 
    // Test loop
    always @ (posedge clk) begin
@@ -50,7 +54,7 @@ module t (/*AUTOARG*/
 	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
 	 if (crc !== 64'hc77bb9b3784ea091) $stop;
 	 // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h14f90df4eab2c499
+`define EXPECTED_SUM 64'hfb06f31a3805822e
 	 if (sum !== `EXPECTED_SUM) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
@@ -58,3 +62,16 @@ module t (/*AUTOARG*/
    end
 
 endmodule
+
+module t_tri (/*AUTOARG*/
+   // Outputs
+   t2,
+   // Inputs
+   d, oe
+   );
+   output t2;
+   input  d;
+   input  oe;
+   tri1   t2;
+   bufif1 (t2, d, oe);
+endmodule