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Tests: Pass tool to allow ifdefs in VPI C code.
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Wilson Snyder
parent
828fa80afa
commit
ae311200bf
@ -598,15 +598,19 @@ sub new {
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.(($^O eq "darwin" )
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? " -Wl,-undefined,dynamic_lookup"
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: " -export-dynamic")
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.($opt_verbose ? " -DTEST_VERBOSE=1":"")
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." -o $self->{obj_dir}/libvpi.so"],
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tool_c_flags => [],
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# ATSIM
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atsim => 0,
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atsim_define => 'ATSIM',
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atsim_flags => [split(/\s+/,"-c +sv +define+ATSIM"),
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"+sv_dir+$self->{obj_dir}/.athdl_compile"],
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atsim_flags2 => [], # Overridden in some sim files
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atsim_run_flags => [],
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# GHDL
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ghdl => 0,
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ghdl_define => 'GHDL',
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ghdl_work_dir => "$self->{obj_dir}/ghdl_compile",
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ghdl_flags => [($::Debug?"-v":""),
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"--workdir=$self->{obj_dir}/ghdl_compile", ],
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@ -614,29 +618,34 @@ sub new {
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ghdl_run_flags => [],
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# IV
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iv => 0,
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iv_define => 'IVERILOG',
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iv_flags => [split(/\s+/,"+define+IVERILOG -g2012 -o $self->{obj_dir}/simiv")],
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iv_flags2 => [], # Overridden in some sim files
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iv_pli => 0, # need to use pli
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iv_run_flags => [],
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# VCS
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vcs => 0,
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vcs_define => 'VCS',
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vcs_flags => [split(/\s+/,"+vcs+lic+wait +cli -debug_access +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")],
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vcs_flags2 => [], # Overridden in some sim files
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vcs_run_flags => [split(/\s+/,"+vcs+lic_wait")],
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# NC
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nc => 0,
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nc_define => 'NC',
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nc_flags => [split(/\s+/,("+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c "
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.($opt_trace ? " +access+r":"")))],
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nc_flags2 => [], # Overridden in some sim files
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nc_run_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
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# ModelSim
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ms => 0,
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ms_define => 'MS',
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ms_flags => [split(/\s+/, ("-sv -work $self->{obj_dir}/work +define+MS=1 -ccflags \"-DMS=1\""))],
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ms_flags2 => [], # Overridden in some sim files
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ms_pli => 1, # need to use pli
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ms_run_flags => [split(/\s+/,"-lib $self->{obj_dir}/work -c -do 'run -all;quit' ")],
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# XSim
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xsim => 0,
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xsim_define => 'XSIM',
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xsim_flags => [split(/\s+/,("--nolog --sv --define XSIM --work $self->{name}=$self->{obj_dir}/xsim"))],
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xsim_flags2 => [], # Overridden in some sim files
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xsim_run_flags => [split(/\s+/,("--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim"
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@ -645,6 +654,7 @@ sub new {
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# Verilator
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vlt => 0,
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vltmt => 0,
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verilator_define => 'VERILATOR',
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verilator_flags => ["-cc",
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"-Mdir $self->{obj_dir}",
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"-OD", # As currently disabled unless -O3
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@ -957,6 +967,7 @@ sub compile {
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}
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if ($param{atsim}) {
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$param{tool_define} ||= $param{atsim_define};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log",
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fails=>$param{fails},
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@ -971,6 +982,7 @@ sub compile {
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]);
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}
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elsif ($param{ghdl}) {
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$param{tool_define} ||= $param{ghdl_define};
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mkdir $self->{ghdl_work_dir};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log",
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@ -989,6 +1001,7 @@ sub compile {
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]);
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}
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elsif ($param{vcs}) {
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$param{tool_define} ||= $param{vcs_define};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log",
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fails=>$param{fails},
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@ -1003,6 +1016,7 @@ sub compile {
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]);
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}
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elsif ($param{nc}) {
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$param{tool_define} ||= $param{nc_define};
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$self->_make_top();
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my @more_args;
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if ($self->vhdl) {
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@ -1024,6 +1038,7 @@ sub compile {
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]);
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}
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elsif ($param{ms}) {
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$param{tool_define} ||= $param{ms_define};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/ms_compile.log",
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fails=>$param{fails},
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@ -1039,6 +1054,7 @@ sub compile {
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]);
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}
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elsif ($param{iv}) {
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$param{tool_define} ||= $param{iv_define};
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$self->_make_top();
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my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"),
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@{$param{iv_flags}},
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@ -1055,6 +1071,7 @@ sub compile {
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cmd=>\@cmd);
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}
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elsif ($param{xsim}) {
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$param{tool_define} ||= $param{xsim_define};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log",
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fails=>$param{fails},
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@ -1069,6 +1086,7 @@ sub compile {
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]);
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}
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elsif ($param{vlt_all}) {
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$param{tool_define} ||= $param{verilator_define};
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if ($self->sc && !$self->have_sc) {
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$self->skip("Test requires SystemC; ignore error since not installed\n");
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@ -1166,7 +1184,9 @@ sub compile {
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if ($param{make_pli}) {
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$self->oprint("Compile vpi\n") if $self->{verbose};
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my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, "-DIS_VPI", $ENV{CFLAGS},
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my @cmd = ($ENV{CXX}, @{$param{pli_flags}},
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"-D".$param{tool_define},
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"-DIS_VPI", ($ENV{CFLAGS}||''),
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"$self->{t_dir}/$self->{pli_filename}");
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$self->_run(logfile=>"$self->{obj_dir}/pli_compile.log",
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@ -36,7 +36,11 @@ public:
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void release() {
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if (m_handle && m_freeit) {
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// Below not VL_DO_DANGLING so is portable
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#ifdef IVERILOG
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vpi_free_object(m_handle);
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#else
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vpi_release_handle(m_handle);
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#endif
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m_handle = NULL;
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}
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}
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@ -35,9 +35,6 @@
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#include "TestSimulator.h"
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#include "TestVpi.h"
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#define TEST_MSG \
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if (0) printf
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unsigned int main_time = 0;
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unsigned int callback_count_time1 = 3;
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unsigned int callback_count_time2 = 4;
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@ -119,6 +116,10 @@ static int _time_cb2(p_cb_data cb_data) {
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}
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static int _start_of_sim_cb(p_cb_data cb_data) {
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#ifdef TEST_VERBOSE
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printf("-_start_of_sim_cb\n");
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#endif
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t_cb_data cb_data_n1, cb_data_n2;
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bzero(&cb_data_n1, sizeof(cb_data_n1));
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bzero(&cb_data_n2, sizeof(cb_data_n2));
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@ -8,14 +8,9 @@
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module t (/*AUTOARG*/
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// Inputs
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input clk
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clk
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);
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`ifndef VERILATOR
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reg clk_r = 0;
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always #10 clk_r = ~clk_r;
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assign clk = clk_r;
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`endif
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input clk;
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reg [31:0] count /*verilator public_flat_rd */;
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@ -35,9 +35,6 @@
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#include "TestSimulator.h"
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#include "TestVpi.h"
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#define TEST_MSG \
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if (0) printf
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unsigned int main_time = 0;
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unsigned int callback_count_zero_time = 0;
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unsigned int callback_count_start_of_sim = 0;
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@ -62,6 +59,10 @@ static int _zero_time_cb(p_cb_data cb_data) {
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}
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static int _start_of_sim_cb(p_cb_data cb_data) {
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#ifdef TEST_VERBOSE
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printf("-_start_of_sim_cb\n");
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#endif
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t_cb_data cb_data_n;
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bzero(&cb_data_n, sizeof(cb_data_n));
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s_vpi_time t;
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@ -11,7 +11,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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scenarios(simulator => 1);
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compile(
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make_top_shell => 0,
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make_main => 0,
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make_pli => 1,
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sim_time => 2100,
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@ -8,14 +8,9 @@
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module t (/*AUTOARG*/
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// Inputs
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input clk
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clk
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);
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`ifndef VERILATOR
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reg clk_r = 0;
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always #10 clk_r = ~clk_r;
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assign clk = clk_r;
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`endif
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input clk;
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reg [31:0] count /*verilator public_flat_rd */;
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