diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 94e2cd594..8f349fe52 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -598,15 +598,19 @@ sub new {
                       .(($^O eq "darwin" )
                         ? " -Wl,-undefined,dynamic_lookup"
                         : " -export-dynamic")
+                      .($opt_verbose ? " -DTEST_VERBOSE=1":"")
                       ." -o $self->{obj_dir}/libvpi.so"],
+        tool_c_flags => [],
         # ATSIM
         atsim => 0,
+        atsim_define => 'ATSIM',
         atsim_flags => [split(/\s+/,"-c +sv +define+ATSIM"),
                         "+sv_dir+$self->{obj_dir}/.athdl_compile"],
         atsim_flags2 => [],  # Overridden in some sim files
         atsim_run_flags => [],
         # GHDL
         ghdl => 0,
+        ghdl_define => 'GHDL',
         ghdl_work_dir => "$self->{obj_dir}/ghdl_compile",
         ghdl_flags => [($::Debug?"-v":""),
                        "--workdir=$self->{obj_dir}/ghdl_compile", ],
@@ -614,29 +618,34 @@ sub new {
         ghdl_run_flags => [],
         # IV
         iv => 0,
+        iv_define => 'IVERILOG',
         iv_flags => [split(/\s+/,"+define+IVERILOG -g2012 -o $self->{obj_dir}/simiv")],
         iv_flags2 => [],  # Overridden in some sim files
         iv_pli => 0,  # need to use pli
         iv_run_flags => [],
         # VCS
         vcs => 0,
+        vcs_define => 'VCS',
         vcs_flags => [split(/\s+/,"+vcs+lic+wait +cli -debug_access +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")],
         vcs_flags2 => [],  # Overridden in some sim files
         vcs_run_flags => [split(/\s+/,"+vcs+lic_wait")],
         # NC
         nc => 0,
+        nc_define => 'NC',
         nc_flags => [split(/\s+/,("+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c "
                                   .($opt_trace ? " +access+r":"")))],
         nc_flags2 => [],  # Overridden in some sim files
         nc_run_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
         # ModelSim
         ms => 0,
+        ms_define => 'MS',
         ms_flags => [split(/\s+/, ("-sv -work $self->{obj_dir}/work +define+MS=1 -ccflags \"-DMS=1\""))],
         ms_flags2 => [],  # Overridden in some sim files
         ms_pli => 1,  # need to use pli
         ms_run_flags => [split(/\s+/,"-lib $self->{obj_dir}/work -c -do 'run -all;quit' ")],
         # XSim
         xsim => 0,
+        xsim_define => 'XSIM',
         xsim_flags => [split(/\s+/,("--nolog --sv --define XSIM --work $self->{name}=$self->{obj_dir}/xsim"))],
         xsim_flags2 => [],  # Overridden in some sim files
         xsim_run_flags => [split(/\s+/,("--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim"
@@ -645,6 +654,7 @@ sub new {
         # Verilator
         vlt => 0,
         vltmt => 0,
+        verilator_define => 'VERILATOR',
         verilator_flags => ["-cc",
                             "-Mdir $self->{obj_dir}",
                             "-OD",  # As currently disabled unless -O3
@@ -957,6 +967,7 @@ sub compile {
     }
 
     if ($param{atsim}) {
+        $param{tool_define} ||= $param{atsim_define};
         $self->_make_top();
         $self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log",
                     fails=>$param{fails},
@@ -971,6 +982,7 @@ sub compile {
                           ]);
     }
     elsif ($param{ghdl}) {
+        $param{tool_define} ||= $param{ghdl_define};
         mkdir $self->{ghdl_work_dir};
         $self->_make_top();
         $self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log",
@@ -989,6 +1001,7 @@ sub compile {
                           ]);
     }
     elsif ($param{vcs}) {
+        $param{tool_define} ||= $param{vcs_define};
         $self->_make_top();
         $self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log",
                     fails=>$param{fails},
@@ -1003,6 +1016,7 @@ sub compile {
                           ]);
     }
     elsif ($param{nc}) {
+        $param{tool_define} ||= $param{nc_define};
         $self->_make_top();
         my @more_args;
         if ($self->vhdl) {
@@ -1024,6 +1038,7 @@ sub compile {
                           ]);
     }
     elsif ($param{ms}) {
+        $param{tool_define} ||= $param{ms_define};
         $self->_make_top();
         $self->_run(logfile=>"$self->{obj_dir}/ms_compile.log",
                     fails=>$param{fails},
@@ -1039,6 +1054,7 @@ sub compile {
                           ]);
     }
     elsif ($param{iv}) {
+        $param{tool_define} ||= $param{iv_define};
         $self->_make_top();
         my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"),
                    @{$param{iv_flags}},
@@ -1055,6 +1071,7 @@ sub compile {
                     cmd=>\@cmd);
     }
     elsif ($param{xsim}) {
+        $param{tool_define} ||= $param{xsim_define};
         $self->_make_top();
         $self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log",
                     fails=>$param{fails},
@@ -1069,6 +1086,7 @@ sub compile {
                           ]);
     }
     elsif ($param{vlt_all}) {
+        $param{tool_define} ||= $param{verilator_define};
 
         if ($self->sc && !$self->have_sc) {
             $self->skip("Test requires SystemC; ignore error since not installed\n");
@@ -1166,7 +1184,9 @@ sub compile {
 
     if ($param{make_pli}) {
         $self->oprint("Compile vpi\n") if $self->{verbose};
-        my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, "-DIS_VPI", $ENV{CFLAGS},
+        my @cmd = ($ENV{CXX}, @{$param{pli_flags}},
+                   "-D".$param{tool_define},
+                   "-DIS_VPI", ($ENV{CFLAGS}||''),
                    "$self->{t_dir}/$self->{pli_filename}");
 
         $self->_run(logfile=>"$self->{obj_dir}/pli_compile.log",
diff --git a/test_regress/t/TestVpi.h b/test_regress/t/TestVpi.h
index 155d924f1..e783b9660 100644
--- a/test_regress/t/TestVpi.h
+++ b/test_regress/t/TestVpi.h
@@ -36,7 +36,11 @@ public:
     void release() {
         if (m_handle && m_freeit) {
             // Below not VL_DO_DANGLING so is portable
+#ifdef IVERILOG
+            vpi_free_object(m_handle);
+#else
             vpi_release_handle(m_handle);
+#endif
             m_handle = NULL;
         }
     }
diff --git a/test_regress/t/t_vpi_time_cb.cpp b/test_regress/t/t_vpi_time_cb.cpp
index fea6e218d..f7b351642 100644
--- a/test_regress/t/t_vpi_time_cb.cpp
+++ b/test_regress/t/t_vpi_time_cb.cpp
@@ -35,9 +35,6 @@
 #include "TestSimulator.h"
 #include "TestVpi.h"
 
-#define TEST_MSG \
-    if (0) printf
-
 unsigned int main_time = 0;
 unsigned int callback_count_time1 = 3;
 unsigned int callback_count_time2 = 4;
@@ -119,6 +116,10 @@ static int _time_cb2(p_cb_data cb_data) {
 }
 
 static int _start_of_sim_cb(p_cb_data cb_data) {
+#ifdef TEST_VERBOSE
+    printf("-_start_of_sim_cb\n");
+#endif
+
     t_cb_data cb_data_n1, cb_data_n2;
     bzero(&cb_data_n1, sizeof(cb_data_n1));
     bzero(&cb_data_n2, sizeof(cb_data_n2));
diff --git a/test_regress/t/t_vpi_time_cb.v b/test_regress/t/t_vpi_time_cb.v
index 846302d8a..1ac2d001f 100644
--- a/test_regress/t/t_vpi_time_cb.v
+++ b/test_regress/t/t_vpi_time_cb.v
@@ -8,14 +8,9 @@
 
 module t (/*AUTOARG*/
    // Inputs
-   input clk
+   clk
    );
-
-`ifndef VERILATOR
-   reg   clk_r = 0;
-   always #10 clk_r = ~clk_r;
-   assign clk = clk_r;
-`endif
+   input clk;
 
    reg [31:0]      count        /*verilator public_flat_rd */;
 
diff --git a/test_regress/t/t_vpi_zero_time_cb.cpp b/test_regress/t/t_vpi_zero_time_cb.cpp
index 7127f2d47..b0e8cb0da 100644
--- a/test_regress/t/t_vpi_zero_time_cb.cpp
+++ b/test_regress/t/t_vpi_zero_time_cb.cpp
@@ -35,9 +35,6 @@
 #include "TestSimulator.h"
 #include "TestVpi.h"
 
-#define TEST_MSG \
-    if (0) printf
-
 unsigned int main_time = 0;
 unsigned int callback_count_zero_time = 0;
 unsigned int callback_count_start_of_sim = 0;
@@ -62,6 +59,10 @@ static int _zero_time_cb(p_cb_data cb_data) {
 }
 
 static int _start_of_sim_cb(p_cb_data cb_data) {
+#ifdef TEST_VERBOSE
+    printf("-_start_of_sim_cb\n");
+#endif
+
     t_cb_data cb_data_n;
     bzero(&cb_data_n, sizeof(cb_data_n));
     s_vpi_time t;
diff --git a/test_regress/t/t_vpi_zero_time_cb.pl b/test_regress/t/t_vpi_zero_time_cb.pl
index 7906bed68..d2e13ef9c 100755
--- a/test_regress/t/t_vpi_zero_time_cb.pl
+++ b/test_regress/t/t_vpi_zero_time_cb.pl
@@ -11,7 +11,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    make_top_shell => 0,
     make_main => 0,
     make_pli => 1,
     sim_time => 2100,
diff --git a/test_regress/t/t_vpi_zero_time_cb.v b/test_regress/t/t_vpi_zero_time_cb.v
index 846302d8a..1ac2d001f 100644
--- a/test_regress/t/t_vpi_zero_time_cb.v
+++ b/test_regress/t/t_vpi_zero_time_cb.v
@@ -8,14 +8,9 @@
 
 module t (/*AUTOARG*/
    // Inputs
-   input clk
+   clk
    );
-
-`ifndef VERILATOR
-   reg   clk_r = 0;
-   always #10 clk_r = ~clk_r;
-   assign clk = clk_r;
-`endif
+   input clk;
 
    reg [31:0]      count        /*verilator public_flat_rd */;