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Tests: Add output wire check.

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This commit is contained in:
Wilson Snyder 2019-12-02 20:38:43 -05:00
parent 559852f60b
commit ac4f0da9ee
8 changed files with 47 additions and 15 deletions
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14
test_regress/t/t_wire_beh1364_bad.out
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@ -1,13 +1,21 @@
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
: ... In instance t : ... In instance t
w = '0; w = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
: ... In instance t : ... In instance t
o = '0; o = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
: ... In instance t : ... In instance t
oa = '0; oa = '0;
^~ ^~
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
: ... In instance t
wo = '0;
^~
%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
: ... In instance t
woa = '0;
^~~
%Error: Exiting due to %Error: Exiting due to

6
test_regress/t/t_wire_beh1364_bad.v
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@ -5,7 +5,7 @@
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Outputs // Outputs
o, oa, ro, roa o, oa, ro, roa, wo, woa
); );
wire w; wire w;
@ -14,6 +14,8 @@ module t (/*AUTOARG*/
output [1:0] oa; output [1:0] oa;
output reg ro; output reg ro;
output reg [1:0] roa; output reg [1:0] roa;
output wire wo;
output wire [1:0] woa;
//1800 only: //1800 only:
//output var vo; //output var vo;
//output var [1:0] voa; //output var [1:0] voa;
@ -22,6 +24,8 @@ module t (/*AUTOARG*/
w = '0; // Error w = '0; // Error
o = '0; // Error o = '0; // Error
oa = '0; // Error oa = '0; // Error
wo = '0; // Error
woa = '0; // Error
r = '0; // Not an error r = '0; // Not an error
ro = '0; // Not an error ro = '0; // Not an error
roa = '0; // Not an error roa = '0; // Not an error

14
test_regress/t/t_wire_beh1800_bad.out
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@ -1,13 +1,21 @@
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
: ... In instance t : ... In instance t
w = '0; w = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
: ... In instance t : ... In instance t
o = '0; o = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
: ... In instance t : ... In instance t
oa = '0; oa = '0;
^~ ^~
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
: ... In instance t
wo = '0;
^~
%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
: ... In instance t
woa = '0;
^~~
%Error: Exiting due to %Error: Exiting due to

6
test_regress/t/t_wire_beh1800_bad.v
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@ -5,7 +5,7 @@
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Outputs // Outputs
o, oa, ro, roa, vo, voa o, oa, ro, roa, wo, woa, vo, voa
); );
wire w; wire w;
@ -14,6 +14,8 @@ module t (/*AUTOARG*/
output [1:0] oa; output [1:0] oa;
output reg ro; output reg ro;
output reg [1:0] roa; output reg [1:0] roa;
output wire wo;
output wire [1:0] woa;
// 1800 only // 1800 only
output var vo; output var vo;
output var [1:0] voa; output var [1:0] voa;
@ -22,6 +24,8 @@ module t (/*AUTOARG*/
w = '0; // Error w = '0; // Error
o = '0; // Error o = '0; // Error
oa = '0; // Error oa = '0; // Error
wo = '0; // Error
woa = '0; // Error
r = '0; // Not an error r = '0; // Not an error
ro = '0; // Not an error ro = '0; // Not an error
roa = '0; // Not an error roa = '0; // Not an error

6
test_regress/t/t_wire_behp1364_bad.out
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@ -1,12 +1,12 @@
%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
: ... In instance t : ... In instance t
w = '0; w = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
: ... In instance t : ... In instance t
o = '0; o = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
: ... In instance t : ... In instance t
oa = '0; oa = '0;
^~ ^~

6
test_regress/t/t_wire_behp1364_bad.v
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@ -7,7 +7,9 @@ module t (
output o, output o,
output [1:0] oa, output [1:0] oa,
output reg ro, output reg ro,
output reg [1:0] roa output reg [1:0] roa,
output wire wo,
output wire [1:0] woa
//1800 only: //1800 only:
//output var vo; //output var vo;
//output var [1:0] voa; //output var [1:0] voa;
@ -20,6 +22,8 @@ module t (
w = '0; // Error w = '0; // Error
o = '0; // Error o = '0; // Error
oa = '0; // Error oa = '0; // Error
wo = '0; // Error
woa = '0; // Error
r = '0; // Not an error r = '0; // Not an error
ro = '0; // Not an error ro = '0; // Not an error
roa = '0; // Not an error roa = '0; // Not an error

6
test_regress/t/t_wire_behp1800_bad.out
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@ -1,12 +1,12 @@
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
: ... In instance t : ... In instance t
w = '0; w = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o' %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
: ... In instance t : ... In instance t
o = '0; o = '0;
^ ^
%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa' %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
: ... In instance t : ... In instance t
oa = '0; oa = '0;
^~ ^~

4
test_regress/t/t_wire_behp1800_bad.v
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@ -8,6 +8,8 @@ module t (
output [1:0] oa, output [1:0] oa,
output reg ro, output reg ro,
output reg [1:0] roa, output reg [1:0] roa,
output wire wo,
output wire [1:0] woa,
// 1800 only // 1800 only
output var vo, output var vo,
output var [1:0] voa output var [1:0] voa
@ -20,6 +22,8 @@ module t (
w = '0; // Error w = '0; // Error
o = '0; // Error o = '0; // Error
oa = '0; // Error oa = '0; // Error
wo = '0; // Error
woa = '0; // Error
r = '0; // Not an error r = '0; // Not an error
ro = '0; // Not an error ro = '0; // Not an error
roa = '0; // Not an error roa = '0; // Not an error