diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out
index 6964a527b..b8587e157 100644
--- a/test_regress/t/t_wire_beh1364_bad.out
+++ b/test_regress/t/t_wire_beh1364_bad.out
@@ -1,13 +1,21 @@
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
                                              : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
                                              : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
                                              : ... In instance t
       oa = '0;   
       ^~
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
+                                             : ... In instance t
+      wo = '0;   
+      ^~
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
+                                             : ... In instance t
+      woa = '0;   
+      ^~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_wire_beh1364_bad.v b/test_regress/t/t_wire_beh1364_bad.v
index daa6d89de..c88bbe3bc 100644
--- a/test_regress/t/t_wire_beh1364_bad.v
+++ b/test_regress/t/t_wire_beh1364_bad.v
@@ -5,7 +5,7 @@
 
 module t (/*AUTOARG*/
    // Outputs
-   o, oa, ro, roa
+   o, oa, ro, roa, wo, woa
    );
 
    wire w;
@@ -14,6 +14,8 @@ module t (/*AUTOARG*/
    output [1:0] oa;
    output reg ro;
    output reg [1:0] roa;
+   output wire wo;
+   output wire [1:0] woa;
    //1800 only:
    //output var vo;
    //output var [1:0] voa;
@@ -22,6 +24,8 @@ module t (/*AUTOARG*/
       w = '0;  // Error
       o = '0;  // Error
       oa = '0;  // Error
+      wo = '0;  // Error
+      woa = '0;  // Error
       r = '0;  // Not an error
       ro = '0;  // Not an error
       roa = '0;  // Not an error
diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out
index b3354704a..296b99738 100644
--- a/test_regress/t/t_wire_beh1800_bad.out
+++ b/test_regress/t/t_wire_beh1800_bad.out
@@ -1,13 +1,21 @@
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
                                              : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
                                              : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
                                              : ... In instance t
       oa = '0;   
       ^~
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'wo'
+                                             : ... In instance t
+      wo = '0;   
+      ^~
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'woa'
+                                             : ... In instance t
+      woa = '0;   
+      ^~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_wire_beh1800_bad.v b/test_regress/t/t_wire_beh1800_bad.v
index 12b814840..baddf265e 100644
--- a/test_regress/t/t_wire_beh1800_bad.v
+++ b/test_regress/t/t_wire_beh1800_bad.v
@@ -5,7 +5,7 @@
 
 module t (/*AUTOARG*/
    // Outputs
-   o, oa, ro, roa, vo, voa
+   o, oa, ro, roa, wo, woa, vo, voa
    );
 
    wire w;
@@ -14,6 +14,8 @@ module t (/*AUTOARG*/
    output [1:0] oa;
    output reg ro;
    output reg [1:0] roa;
+   output wire wo;
+   output wire [1:0] woa;
    // 1800 only
    output var vo;
    output var [1:0] voa;
@@ -22,6 +24,8 @@ module t (/*AUTOARG*/
       w = '0;  // Error
       o = '0;  // Error
       oa = '0;  // Error
+      wo = '0;  // Error
+      woa = '0;  // Error
       r = '0;  // Not an error
       ro = '0;  // Not an error
       roa = '0;  // Not an error
diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out
index 144c960d0..f0f1af40a 100644
--- a/test_regress/t/t_wire_behp1364_bad.out
+++ b/test_regress/t/t_wire_behp1364_bad.out
@@ -1,12 +1,12 @@
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
                                               : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
                                               : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
                                               : ... In instance t
       oa = '0;   
       ^~
diff --git a/test_regress/t/t_wire_behp1364_bad.v b/test_regress/t/t_wire_behp1364_bad.v
index 0af6c1eb0..a80d4d6e2 100644
--- a/test_regress/t/t_wire_behp1364_bad.v
+++ b/test_regress/t/t_wire_behp1364_bad.v
@@ -7,7 +7,9 @@ module t (
    output o,
    output [1:0] oa,
    output reg ro,
-   output reg [1:0] roa
+   output reg [1:0] roa,
+   output wire wo,
+   output wire [1:0] woa
    //1800 only:
    //output var vo;
    //output var [1:0] voa;
@@ -20,6 +22,8 @@ module t (
       w = '0;  // Error
       o = '0;  // Error
       oa = '0;  // Error
+      wo = '0;  // Error
+      woa = '0;  // Error
       r = '0;  // Not an error
       ro = '0;  // Not an error
       roa = '0;  // Not an error
diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out
index 21d612cfa..4db8bea6a 100644
--- a/test_regress/t/t_wire_behp1800_bad.out
+++ b/test_regress/t/t_wire_behp1800_bad.out
@@ -1,12 +1,12 @@
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
                                               : ... In instance t
       w = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
                                               : ... In instance t
       o = '0;   
       ^
-%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
                                               : ... In instance t
       oa = '0;   
       ^~
diff --git a/test_regress/t/t_wire_behp1800_bad.v b/test_regress/t/t_wire_behp1800_bad.v
index 773d0a1b9..e2d890e7f 100644
--- a/test_regress/t/t_wire_behp1800_bad.v
+++ b/test_regress/t/t_wire_behp1800_bad.v
@@ -8,6 +8,8 @@ module t (
    output [1:0] oa,
    output reg ro,
    output reg [1:0] roa,
+   output wire wo,
+   output wire [1:0] woa,
    // 1800 only
    output var vo,
    output var [1:0] voa
@@ -20,6 +22,8 @@ module t (
       w = '0;  // Error
       o = '0;  // Error
       oa = '0;  // Error
+      wo = '0;  // Error
+      woa = '0;  // Error
       r = '0;  // Not an error
       ro = '0;  // Not an error
       roa = '0;  // Not an error