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Commentary: Changes update
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Changes
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Changes
@ -14,15 +14,17 @@ Verilator 5.021 devel
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**Minor:**
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* Add predicted stack overflow warning (#4799).
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* Add +verilator+coverage+file runtime option.
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* Add --runtime-debug for Verilated executable runtime debugging.
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* Add `+verilator+coverage+file` runtime option.
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* Add `--runtime-debug` for Verilated executable runtime debugging.
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* Add `--decorations node` for inserting debug comments into emitted code.
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* Add `unroll_disable` and `unroll_full` loop control metacomments (#3260). [Jiaxun Yang]
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* Add --json-only and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.]
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* Add `--json-only` and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.]
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* Add `--valgrind` switch (#4828). [Szymon Gizler]
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* Remove deprecated 32-bit pointer mode (`gcc -m32`).
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* Deprecate --xml-only and XML dumping (#4715) (#4831).
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* Change zero replication width error to ZEROREPL warning (#4753) (#4762). [Pengcheng Xu]
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* Support dumping coverage with --main.
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* Support dumping coverage with `--main`.
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* Support dumping DFG patterns with `--stats` (#4889). [Geza Lore]
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* Support `vpiConstType` in `vpi_get_str()` (#4797). [Marlon James]
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* Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon]
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* Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon]
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@ -46,9 +48,14 @@ Verilator 5.021 devel
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* Fix NOT when checking EQ/NEQ under AND/OR tree (#4857) (#4863). [Yutetsu TAKATSUKASA]
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* Fix tracing chandles (#4860). [Nathan Graybeal]
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* Fix $fwrite of null (#4862). [Jose Tejada]
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* Fix -fno-const-bit-op-tree wrong runtime result (#4864) (#4867). [Yutetsu TAKATSUKASA]
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* Fix SystemC biguint sign desynchronization (#4870). [Bartłomiej Chmiel]
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* Fix incorrect temporary insertion in loop conditions with statements (#4873). [Geza Lore]
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* Fix timing with expr on assign LHS (#4880). [Krzysztof Bieganski, Antmicro Ltd.]
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* Fix assertion for unique case (#4892). [Yutetsu TAKATSUKASA]
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* Fix GCC tautological-compare warnings.
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* Fix compile error on structs with queues (and ignore toggle coverage on queues).
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* Fix toggle coverage dataDeclp error on multi-edge driven signals.
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* Fix toggle coverage error on multi-edge driven signals.
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Verilator 5.020 2024-01-01
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@ -66,9 +66,9 @@ executable performs the design simulation. Verilator also supports linking
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Verilated generated libraries, optionally encrypted, into other simulators.
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Verilator may not be the best choice if you are expecting a full-featured
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replacement for a closed-source Verilog simulator, needs SDF annotation,
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replacement for a closed-source Verilog simulator, need SDF annotation,
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mixed-signal simulation, or are doing a quick class project (we recommend
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`Icarus Verilog`_ for classwork.) However, if you are looking for a path
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`Icarus Verilog`_ for classwork). However, if you are looking for a path
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to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
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designs, Verilator is the tool for you.
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@ -80,12 +80,12 @@ Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
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Verilator compiles your code into a much faster optimized and optionally
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thread-partitioned model, which is in turn wrapped inside a C++/SystemC
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module. The results are a compiled Verilog model that executes even on a
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single-thread over 10x faster than standalone SystemC, and on a single
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single thread over 10x faster than standalone SystemC, and on a single
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thread is about 100 times faster than interpreted Verilog simulators such
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as `Icarus Verilog`_. Another 2-10x speedup might be gained from
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multithreading (yielding 200-1000x total over interpreted simulators).
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Verilator has typically similar or better performance versus the
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Verilator has typically similar or better performance versus
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closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator,
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Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
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Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
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@ -1777,8 +1777,8 @@ Summary:
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the Verilator Internals manual. Be aware that the JSON
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format is still evolving; there will be some changes in future versions.
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This option disables some more agressive transformations and dumps only the
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final state of the AST.
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This option disables some more aggressive transformations and dumps only
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the final state of the AST.
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.. option:: --json-only-meta-output <filename>
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@ -1792,12 +1792,12 @@ Summary:
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.. option:: --no-json-edit-nums
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Don't dump editNum in .tree.json files. This may make the file more
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Don't dump edit number in .tree.json files. This may make the file more
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run-to-run stable for easier comparison.
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.. option:: --no-json-ids
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Don't use short identifiers instead of adresses/paths in .tree.json.
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Don't use short identifiers instead of addresses/paths in .tree.json.
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.. option:: --xml-only
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@ -23,12 +23,12 @@ resulting model's C++ or SystemC code is output as .cpp and .h files. This
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is referred to as "Verilating", and the process is "to Verilate"; the
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output is a "Verilated" model.
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2. For simulation, a small-user written C++ wrapper file is required, the
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2. For simulation, a small user-written C++ wrapper file is required, the
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"wrapper". This wrapper defines the C++ standard function "main()", which
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instantiates the Verilated model as a C++/SystemC object.
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3. The user C++ wrapper, the files created by Verilator, a "runtime
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library" provided by Verilator, and, if applicable SystemC libraries are
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library" provided by Verilator, and, if applicable, SystemC libraries are
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then compiled using a C++ compiler to create a simulation executable.
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4. The resulting executable will perform the actual simulation during
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@ -180,6 +180,7 @@ Jannis
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Jasen
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Jens
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Jeras
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Jiaxun
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Jiuyang
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Joannou
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Joly
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@ -519,6 +520,7 @@ buildenv
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bv
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bvs
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callValueCbs
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callgrind
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casex
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casez
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casted
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@ -583,6 +585,7 @@ der
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dereference
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desassign
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destructor
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desynchronization
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detections
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dev
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devcontainer
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@ -613,6 +616,7 @@ dut
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dx
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dynarray
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elab
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eliasphanna
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elike
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elsif
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endcase
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@ -733,6 +737,7 @@ ish
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isunbounded
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isunknown
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jobserver
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json
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jwoutersymatra
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killua
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lang
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@ -1020,6 +1025,7 @@ uselib
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utimes
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uwire
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uwires
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valgrind
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vc
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vcd
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vcddiff
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