diff --git a/Changes b/Changes index 8e0870f49..be7240288 100644 --- a/Changes +++ b/Changes @@ -14,15 +14,17 @@ Verilator 5.021 devel **Minor:** * Add predicted stack overflow warning (#4799). -* Add +verilator+coverage+file runtime option. -* Add --runtime-debug for Verilated executable runtime debugging. +* Add `+verilator+coverage+file` runtime option. +* Add `--runtime-debug` for Verilated executable runtime debugging. * Add `--decorations node` for inserting debug comments into emitted code. * Add `unroll_disable` and `unroll_full` loop control metacomments (#3260). [Jiaxun Yang] -* Add --json-only and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.] +* Add `--json-only` and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.] +* Add `--valgrind` switch (#4828). [Szymon Gizler] * Remove deprecated 32-bit pointer mode (`gcc -m32`). * Deprecate --xml-only and XML dumping (#4715) (#4831). * Change zero replication width error to ZEROREPL warning (#4753) (#4762). [Pengcheng Xu] -* Support dumping coverage with --main. +* Support dumping coverage with `--main`. +* Support dumping DFG patterns with `--stats` (#4889). [Geza Lore] * Support `vpiConstType` in `vpi_get_str()` (#4797). [Marlon James] * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] @@ -46,9 +48,14 @@ Verilator 5.021 devel * Fix NOT when checking EQ/NEQ under AND/OR tree (#4857) (#4863). [Yutetsu TAKATSUKASA] * Fix tracing chandles (#4860). [Nathan Graybeal] * Fix $fwrite of null (#4862). [Jose Tejada] +* Fix -fno-const-bit-op-tree wrong runtime result (#4864) (#4867). [Yutetsu TAKATSUKASA] +* Fix SystemC biguint sign desynchronization (#4870). [Bartłomiej Chmiel] +* Fix incorrect temporary insertion in loop conditions with statements (#4873). [Geza Lore] +* Fix timing with expr on assign LHS (#4880). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix assertion for unique case (#4892). [Yutetsu TAKATSUKASA] * Fix GCC tautological-compare warnings. * Fix compile error on structs with queues (and ignore toggle coverage on queues). -* Fix toggle coverage dataDeclp error on multi-edge driven signals. +* Fix toggle coverage error on multi-edge driven signals. Verilator 5.020 2024-01-01 diff --git a/README.rst b/README.rst index 6fb7c5e4d..c5bfe2b5d 100644 --- a/README.rst +++ b/README.rst @@ -66,9 +66,9 @@ executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full-featured -replacement for a closed-source Verilog simulator, needs SDF annotation, +replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend -`Icarus Verilog`_ for classwork.) However, if you are looking for a path +`Icarus Verilog`_ for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you. @@ -80,12 +80,12 @@ Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a -single-thread over 10x faster than standalone SystemC, and on a single +single thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as `Icarus Verilog`_. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). -Verilator has typically similar or better performance versus the +Verilator has typically similar or better performance versus closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index f2ef8b557..70099b8d3 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1777,8 +1777,8 @@ Summary: the Verilator Internals manual. Be aware that the JSON format is still evolving; there will be some changes in future versions. - This option disables some more agressive transformations and dumps only the - final state of the AST. + This option disables some more aggressive transformations and dumps only + the final state of the AST. .. option:: --json-only-meta-output @@ -1792,12 +1792,12 @@ Summary: .. option:: --no-json-edit-nums - Don't dump editNum in .tree.json files. This may make the file more + Don't dump edit number in .tree.json files. This may make the file more run-to-run stable for easier comparison. .. option:: --no-json-ids - Don't use short identifiers instead of adresses/paths in .tree.json. + Don't use short identifiers instead of addresses/paths in .tree.json. .. option:: --xml-only diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst index 3a6a8b7bd..002ef8b45 100644 --- a/docs/guide/overview.rst +++ b/docs/guide/overview.rst @@ -23,12 +23,12 @@ resulting model's C++ or SystemC code is output as .cpp and .h files. This is referred to as "Verilating", and the process is "to Verilate"; the output is a "Verilated" model. -2. For simulation, a small-user written C++ wrapper file is required, the +2. For simulation, a small user-written C++ wrapper file is required, the "wrapper". This wrapper defines the C++ standard function "main()", which instantiates the Verilated model as a C++/SystemC object. 3. The user C++ wrapper, the files created by Verilator, a "runtime -library" provided by Verilator, and, if applicable SystemC libraries are +library" provided by Verilator, and, if applicable, SystemC libraries are then compiled using a C++ compiler to create a simulation executable. 4. The resulting executable will perform the actual simulation during diff --git a/docs/spelling.txt b/docs/spelling.txt index edb4c1bcc..7b981c76c 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -180,6 +180,7 @@ Jannis Jasen Jens Jeras +Jiaxun Jiuyang Joannou Joly @@ -519,6 +520,7 @@ buildenv bv bvs callValueCbs +callgrind casex casez casted @@ -583,6 +585,7 @@ der dereference desassign destructor +desynchronization detections dev devcontainer @@ -613,6 +616,7 @@ dut dx dynarray elab +eliasphanna elike elsif endcase @@ -733,6 +737,7 @@ ish isunbounded isunknown jobserver +json jwoutersymatra killua lang @@ -1020,6 +1025,7 @@ uselib utimes uwire uwires +valgrind vc vcd vcddiff