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Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1028 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-04-14 21:47:39 +00:00
parent a9281f2c37
commit a02e2e25bb
3 changed files with 18 additions and 2 deletions
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4
Changes
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@ -7,7 +7,9 @@ indicates the contributor was also the author of the fix; Thanks!
**** Add error message when modules have duplicate names. [Stefan Thiede] **** Add error message when modules have duplicate names. [Stefan Thiede]
**** Fix "output reg name=expr;" syntax error. [Martin Scharrer] **** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
**** Fix "output reg name=expr;" syntax error. [Martin Scharrer]
**** Fix multiple .v files being read in random order. [Stefan Thiede] **** Fix multiple .v files being read in random order. [Stefan Thiede]

3
src/verilog.y
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@ -851,6 +851,7 @@ senList: senitem { $$ = $1; }
senitem: senitemEdge { $$ = $1; } senitem: senitemEdge { $$ = $1; }
| senitemVar { $$ = $1; } | senitemVar { $$ = $1; }
| '(' senitemVar ')' { $$ = $2; }
; ;
senitemVar: varRefDotBit { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); } senitemVar: varRefDotBit { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); }
@ -858,6 +859,8 @@ senitemVar: varRefDotBit { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE
senitemEdge: yPOSEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$2); } senitemEdge: yPOSEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$2); }
| yNEGEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); } | yNEGEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); }
| yPOSEDGE '(' varRefDotBit ')' { $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$3); }
| yNEGEDGE '(' varRefDotBit ')' { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$3); }
; ;
//************************************************ //************************************************

13
test_regress/t/t_alw_combdly.v
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@ -12,7 +12,7 @@ module t (/*AUTOARG*/
input clk; input clk;
integer cyc; initial cyc=1; integer cyc; initial cyc=1;
reg [31:0] a, b, c; reg [31:0] a, b, c, d, e;
always @ (*) begin // Test Verilog 2001 (*) always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY // verilator lint_off COMBDLY
@ -20,6 +20,14 @@ module t (/*AUTOARG*/
// verilator lint_on COMBDLY // verilator lint_on COMBDLY
end end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin always @ (posedge clk) begin
if (cyc!=0) begin if (cyc!=0) begin
cyc<=cyc+1; cyc<=cyc+1;
@ -30,6 +38,9 @@ module t (/*AUTOARG*/
if (cyc==2) begin if (cyc==2) begin
if (c != 32'hfeedface) $stop; if (c != 32'hfeedface) $stop;
end end
if (cyc==3) begin
if (e != 32'hfeedface) $stop;
end
if (cyc==7) begin if (cyc==7) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;