From a02e2e25bb7a0131e986f62c9e3c8171f3e77bae Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 14 Apr 2008 21:47:39 +0000
Subject: [PATCH] Fix "always @ ((a) or (b))" syntax error. [by Niranjan
 Prabhu]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1028 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 Changes                        |  4 +++-
 src/verilog.y                  |  3 +++
 test_regress/t/t_alw_combdly.v | 13 ++++++++++++-
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/Changes b/Changes
index 5f6bcd63a..421129339 100644
--- a/Changes
+++ b/Changes
@@ -7,7 +7,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Add error message when modules have duplicate names. [Stefan Thiede]
 
-**** Fix "output reg name=expr;" syntax error.  [Martin Scharrer]
+**** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
+
+**** Fix "output reg name=expr;" syntax error. [Martin Scharrer]
 
 **** Fix multiple .v files being read in random order. [Stefan Thiede]
 
diff --git a/src/verilog.y b/src/verilog.y
index 334000e82..d00ba1089 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -851,6 +851,7 @@ senList:	senitem					{ $$ = $1; }
 
 senitem:	senitemEdge				{ $$ = $1; }
 	|	senitemVar				{ $$ = $1; }
+	|	'(' senitemVar ')'			{ $$ = $2; }
 	;
 
 senitemVar:	varRefDotBit				{ $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); }
@@ -858,6 +859,8 @@ senitemVar:	varRefDotBit				{ $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE
 
 senitemEdge:	yPOSEDGE varRefDotBit			{ $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$2); }
 	|	yNEGEDGE varRefDotBit			{ $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); }
+	|	yPOSEDGE '(' varRefDotBit ')'		{ $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$3); }
+	|	yNEGEDGE '(' varRefDotBit ')'		{ $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$3); }
 	;
 
 //************************************************
diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v
index 9de0143db..c211a1625 100644
--- a/test_regress/t/t_alw_combdly.v
+++ b/test_regress/t/t_alw_combdly.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
-   reg [31:0] a, b, c;
+   reg [31:0] a, b, c, d, e;
 
    always @ (*) begin   // Test Verilog 2001 (*)
       // verilator lint_off COMBDLY
@@ -20,6 +20,14 @@ module t (/*AUTOARG*/
       // verilator lint_on COMBDLY
    end
 
+   always @ (posedge (clk)) begin // always bug 2008/4/18
+      d <= a | b;
+   end
+   always @ ((d)) begin // always bug 2008/4/18
+      e = d;
+   end
+   //always @ ((posedge b) or (a or b)) begin // note both illegal
+
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc<=cyc+1;
@@ -30,6 +38,9 @@ module t (/*AUTOARG*/
 	 if (cyc==2) begin
 	    if (c != 32'hfeedface) $stop;
 	 end
+	 if (cyc==3) begin
+	    if (e != 32'hfeedface) $stop;
+	 end
 	 if (cyc==7) begin
 	    $write("*-* All Finished *-*\n");
 	    $finish;