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Test/cleanup endtable without table

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This commit is contained in:
Wilson Snyder 2022-10-22 12:30:44 -04:00
parent 63df87e220
commit ecfa385f13
7 changed files with 75 additions and 2 deletions
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4
src/verilog.l
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@ -318,7 +318,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"endmodule" { FL; return yENDMODULE; }
"endprimitive" { FL; return yENDPRIMITIVE; }
"endspecify" { FL; return yENDSPECIFY; }
"endtable" { FL; yylval.fl->v3error("Syntax error: ENDTABLE outside of TABLE"); FL_BRK; }
"endtable" { FL; yylval.fl->v3error("Syntax error: 'endtable' outside of 'table'"); FL_BRK; }
"endtask" { FL; return yENDTASK; }
"event" { FL; return yEVENT; }
"for" { FL; return yFOR; }
@ -961,7 +961,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<TABLE>"endtable" { yy_pop_state(); FL; return yENDTABLE; }
<TABLE>"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; }
<TABLE>. { yymore(); }
<TABLE><<EOF>> { FL; yylval.fl->v3error("EOF in TABLE");
<TABLE><<EOF>> { FL; yylval.fl->v3error("EOF in 'table'");
yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
/************************************************************************/

4
test_regress/t/t_udp_tableend_bad.out Normal file
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@ -0,0 +1,4 @@
%Error: t/t_udp_tableend_bad.v:11:4: Syntax error: 'endtable' outside of 'table'
11 | endtable
| ^~~~~~~~
%Error: Exiting due to

20
test_regress/t/t_udp_tableend_bad.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
verilator_flags2 => ["--lint-only --bbox-unsup"],
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

12
test_regress/t/t_udp_tableend_bad.v Normal file
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@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
primitive udp_x (a_bad, b, c_bad);
tri a_bad;
output b;
output c_bad;
endtable // BAD
endprimitive

3
test_regress/t/t_udp_tableeof_bad.out Normal file
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@ -0,0 +1,3 @@
%Error: t/t_udp_tableeof_bad.v:16:1: EOF in 'table'
%Error: t/t_udp_tableeof_bad.v:16:1: syntax error, unexpected end of file, expecting TABLE LINE or endtable
%Error: Cannot continue

20
test_regress/t/t_udp_tableeof_bad.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
verilator_flags2 => ["--lint-only --bbox-unsup"],
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

14
test_regress/t/t_udp_tableeof_bad.v Normal file
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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
primitive udp_x (a_bad, b, c_bad);
tri a_bad;
output b;
output c_bad;
table
//a b
0 : 1;
1 : 0;