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fd2917c928
commit
83081aaefc
@ -5544,7 +5544,7 @@ class WidthVisitor final : public VNVisitor {
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userIterate(modVarp->childDTypep(),
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WidthVP{SELF, BOTH}.p()); // May relink pointed to node
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AstNodeDType* const setDtp = modVarp->childDTypep()->cloneTree(false);
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patternp->childDTypep(setDtp);
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if (!patternp->childDTypep()) patternp->childDTypep(setDtp);
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userIterateChildren(nodep, WidthVP{setDtp, BOTH}.p());
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didWidth = true;
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}
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18
test_regress/t/t_struct_literal_param.py
Executable file
18
test_regress/t/t_struct_literal_param.py
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--debug"])
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test.execute()
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test.passes()
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38
test_regress/t/t_struct_literal_param.v
Normal file
38
test_regress/t/t_struct_literal_param.v
Normal file
@ -0,0 +1,38 @@
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// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Some_pkg;
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typedef struct packed {
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int foo;
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} some_struct_t;
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endpackage
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module sub #(
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parameter Some_pkg::some_struct_t the_some_struct
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) ();
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// finish report
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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sub #(
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.the_some_struct(
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Some_pkg::some_struct_t'{
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foo: 1
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}))
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the_sub ();
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endmodule
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