github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-06 06:37:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: default_nettype is ok

Browse Source
This commit is contained in:
Wilson Snyder 2012-03-24 15:15:32 -04:00
parent 5e3b0bf348
commit 81d83f629f
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test_regress/driver.pl
View File

@ -218,7 +218,7 @@ sub parameter {
elsif ($param =~ /\.pl/) {
push @opt_tests, $param;
}
elsif ($param =~ /^-?-debugi/) {
elsif ($param =~ /^-?(-debugi|-dump-treei)/) {
push @Opt_Driver_Verilator_Flags, $param;
$_Parameter_Next_Level = $param;
}

5
test_regress/t/t_pp_pragmas.v
View File

@ -21,7 +21,7 @@
`default_decay_time infinite
// unsupported (recommended not to): `default_trireg_strength 10
// unsupported: `default_nettype wire
`default_nettype wire
// unsupported: `default_nettype tri
// unsupported: `default_nettype tri0
// unsupported: `default_nettype wand
@ -29,7 +29,7 @@
// unsupported: `default_nettype wor
// unsupported: `default_nettype trior
// unsupported: `default_nettype trireg
// unsupported: `default_nettype none
`default_nettype none
`autoexpand_vectornets
@ -46,7 +46,6 @@
// unsupported: `unconnected_drive pull1
// unsupported: `unconnected_drive pull0
`nounconnected_drive
`nounconnected_drive
`line 100 "hallo.v" 0

4
test_regress/t/t_var_dotted.v
View File

@ -28,7 +28,9 @@ module t (/*AUTOARG*/
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
//$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;