From 81d83f629f068c490d15a5a8cb2bdb828e1acf08 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 24 Mar 2012 15:15:32 -0400
Subject: [PATCH] Tests: default_nettype is ok

---
 test_regress/driver.pl        | 2 +-
 test_regress/t/t_pp_pragmas.v | 5 ++---
 test_regress/t/t_var_dotted.v | 4 +++-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 266872399..02c0f6ef3 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -218,7 +218,7 @@ sub parameter {
     elsif ($param =~ /\.pl/) {
 	push @opt_tests, $param;
     }
-    elsif ($param =~ /^-?-debugi/) {
+    elsif ($param =~ /^-?(-debugi|-dump-treei)/) {
 	push @Opt_Driver_Verilator_Flags, $param;
 	$_Parameter_Next_Level = $param;
     }
diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v
index bdfaf21bc..83ff9c1e7 100644
--- a/test_regress/t/t_pp_pragmas.v
+++ b/test_regress/t/t_pp_pragmas.v
@@ -21,7 +21,7 @@
 `default_decay_time infinite
 // unsupported (recommended not to): `default_trireg_strength 10
 
-// unsupported: `default_nettype wire
+`default_nettype wire
 // unsupported: `default_nettype tri
 // unsupported: `default_nettype tri0
 // unsupported: `default_nettype wand
@@ -29,7 +29,7 @@
 // unsupported: `default_nettype wor
 // unsupported: `default_nettype trior
 // unsupported: `default_nettype trireg
-// unsupported: `default_nettype none
+`default_nettype none
 
 `autoexpand_vectornets
 
@@ -46,7 +46,6 @@
 // unsupported: `unconnected_drive pull1
 // unsupported: `unconnected_drive pull0
 `nounconnected_drive
-`nounconnected_drive
 
 `line 100 "hallo.v" 0
 
diff --git a/test_regress/t/t_var_dotted.v b/test_regress/t/t_var_dotted.v
index 06b3dd255..e693d26c8 100644
--- a/test_regress/t/t_var_dotted.v
+++ b/test_regress/t/t_var_dotted.v
@@ -28,7 +28,9 @@ module t (/*AUTOARG*/
    integer cyc=1;
    always @ (posedge clk) begin
       cyc <= cyc + 1;
-      //$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
+`endif
       if (cyc==2) begin
 	 if (global_cell.globali  != 32'hf00d) $stop;
 	 if (global_cell2.globali != 32'hf22d) $stop;