Remove old unused vlint script

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1036 77ca24e4-aefa-0310-84f0-b9a241c72d87

test_regress/t/t_alw_dly.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -62,7 +62,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_alw_split.v

@@ -130,7 +130,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_alw_splitord.v

@@ -150,7 +150,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_clk_dsp.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -174,7 +174,3 @@ module t_dsppla (/*AUTOARG*/
    end
    
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_clk_gen.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -85,7 +85,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_extend.v

@@ -76,7 +76,3 @@ module t (/*AUTOARG*/
 
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_for_count.v

@@ -98,7 +98,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_for_funcbound.v

@@ -75,7 +75,3 @@ module strings;
       end
    endfunction
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_init_concat.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -85,7 +85,3 @@ module regfile (
    assign rd_guardsok[1] = rd_data[0];
 
 endmodule // regfile
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_array.v

@@ -58,7 +58,3 @@ module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
    `INLINE_MODULE
    wire bitout = (^ onebit) ^ (^ allbits);
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_array_bad.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -28,7 +28,3 @@ endmodule
 module sub (input [7:0] allbits, input onebit, output bitout);
    wire bitout = onebit ^ (^ allbits);
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_ccall.v

@@ -53,7 +53,3 @@ module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output
    wire [63:0] quadout = quad + 64'd1;
 `endif
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_tree.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -103,7 +103,3 @@ module l5 (input [7:0] a, output [7:0] z);
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
    wire [7:0] z `PUBLIC; assign z = a;
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_v2k.v

@@ -67,7 +67,3 @@ module hello(tied_also);
    output reg [3:0] tied_also = 4'b1010;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_inst_wideconst.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -67,7 +67,3 @@ module wide (
    assign zzz = xxx+ { {40{1'b0}},yyy };
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_math_const.v

@@ -103,7 +103,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_math_reverse.v

@@ -81,7 +81,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_math_tri.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -20,7 +20,3 @@ module t (/*AUTOARG*/);
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_mem.v

@@ -66,7 +66,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_order.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -106,7 +106,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_order_a.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -51,7 +51,3 @@ module t_order_a (/*AUTOARG*/
    wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_order_b.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -17,7 +17,3 @@ module t_order_b (/*AUTOARG*/
    wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/t_var_life.v

@@ -103,7 +103,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:

test_regress/t/vlint

@@ -1,12 +0,0 @@
-#!/bin/sh
-# $Id:$
-# DESCRIPTION: Verilator: Invoke linting
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-$DIRPROJECT_PREFIX/bin/vlint --brief \
-    +librescan +libext+.v -y . +incdir+../include \
-    --filt=STMINI,_NETNM,CWCCXX,CSYBEQ,CSEBEQ,NBAJAM,ITENST,STMFOR \
-    $*