From 7b870f4b2a4a9f34097829208375ac348fb968c1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 24 Apr 2008 15:14:40 +0000
Subject: [PATCH] Remove old unused vlint script

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1036 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 test_regress/t/t_alw_dly.v        |  6 +-----
 test_regress/t/t_alw_split.v      |  4 ----
 test_regress/t/t_alw_splitord.v   |  4 ----
 test_regress/t/t_clk_dsp.v        |  6 +-----
 test_regress/t/t_clk_gen.v        |  6 +-----
 test_regress/t/t_extend.v         |  4 ----
 test_regress/t/t_for_count.v      |  4 ----
 test_regress/t/t_for_funcbound.v  |  4 ----
 test_regress/t/t_init_concat.v    |  6 +-----
 test_regress/t/t_inst_array.v     |  4 ----
 test_regress/t/t_inst_array_bad.v |  6 +-----
 test_regress/t/t_inst_ccall.v     |  4 ----
 test_regress/t/t_inst_tree.v      |  6 +-----
 test_regress/t/t_inst_v2k.v       |  4 ----
 test_regress/t/t_inst_wideconst.v |  6 +-----
 test_regress/t/t_math_const.v     |  4 ----
 test_regress/t/t_math_reverse.v   |  4 ----
 test_regress/t/t_math_tri.v       |  6 +-----
 test_regress/t/t_mem.v            |  4 ----
 test_regress/t/t_order.v          |  6 +-----
 test_regress/t/t_order_a.v        |  6 +-----
 test_regress/t/t_order_b.v        |  6 +-----
 test_regress/t/t_var_life.v       |  4 ----
 test_regress/t/vlint              | 12 ------------
 24 files changed, 11 insertions(+), 115 deletions(-)
 delete mode 100755 test_regress/t/vlint

diff --git a/test_regress/t/t_alw_dly.v b/test_regress/t/t_alw_dly.v
index 145ad51bc..1b57f0ac6 100644
--- a/test_regress/t/t_alw_dly.v
+++ b/test_regress/t/t_alw_dly.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -62,7 +62,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v
index 3a588caa1..02ad8bd8e 100644
--- a/test_regress/t/t_alw_split.v
+++ b/test_regress/t/t_alw_split.v
@@ -130,7 +130,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_alw_splitord.v b/test_regress/t/t_alw_splitord.v
index d8e6c2089..8d1146555 100644
--- a/test_regress/t/t_alw_splitord.v
+++ b/test_regress/t/t_alw_splitord.v
@@ -150,7 +150,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v
index f497139a1..a4e593d9f 100644
--- a/test_regress/t/t_clk_dsp.v
+++ b/test_regress/t/t_clk_dsp.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -174,7 +174,3 @@ module t_dsppla (/*AUTOARG*/
    end
    
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v
index ec9e929a5..05aebe44e 100644
--- a/test_regress/t/t_clk_gen.v
+++ b/test_regress/t/t_clk_gen.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -85,7 +85,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v
index fe2228fb6..2dd9368dd 100644
--- a/test_regress/t/t_extend.v
+++ b/test_regress/t/t_extend.v
@@ -76,7 +76,3 @@ module t (/*AUTOARG*/
 
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v
index 663ab0c94..34bd66455 100644
--- a/test_regress/t/t_for_count.v
+++ b/test_regress/t/t_for_count.v
@@ -98,7 +98,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v
index efa74f4bf..354b017bc 100644
--- a/test_regress/t/t_for_funcbound.v
+++ b/test_regress/t/t_for_funcbound.v
@@ -75,7 +75,3 @@ module strings;
       end
    endfunction
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_init_concat.v b/test_regress/t/t_init_concat.v
index e3bd48946..d7b20b0e4 100644
--- a/test_regress/t/t_init_concat.v
+++ b/test_regress/t/t_init_concat.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -85,7 +85,3 @@ module regfile (
    assign rd_guardsok[1] = rd_data[0];
 
 endmodule // regfile
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_array.v b/test_regress/t/t_inst_array.v
index 9ff4edf69..26aafc41e 100644
--- a/test_regress/t/t_inst_array.v
+++ b/test_regress/t/t_inst_array.v
@@ -58,7 +58,3 @@ module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
    `INLINE_MODULE
    wire bitout = (^ onebit) ^ (^ allbits);
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v
index 942a7ed27..8cffa9599 100644
--- a/test_regress/t/t_inst_array_bad.v
+++ b/test_regress/t/t_inst_array_bad.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -28,7 +28,3 @@ endmodule
 module sub (input [7:0] allbits, input onebit, output bitout);
    wire bitout = onebit ^ (^ allbits);
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v
index 489eb54cf..78e2be99e 100644
--- a/test_regress/t/t_inst_ccall.v
+++ b/test_regress/t/t_inst_ccall.v
@@ -53,7 +53,3 @@ module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output
    wire [63:0] quadout = quad + 64'd1;
 `endif
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v
index cba49783e..a288de288 100644
--- a/test_regress/t/t_inst_tree.v
+++ b/test_regress/t/t_inst_tree.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -103,7 +103,3 @@ module l5 (input [7:0] a, output [7:0] z);
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
    wire [7:0] z `PUBLIC; assign z = a;
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v
index debf2a0ac..7e7f00f8f 100644
--- a/test_regress/t/t_inst_v2k.v
+++ b/test_regress/t/t_inst_v2k.v
@@ -67,7 +67,3 @@ module hello(tied_also);
    output reg [3:0] tied_also = 4'b1010;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v
index a5da64d65..3258f12d5 100644
--- a/test_regress/t/t_inst_wideconst.v
+++ b/test_regress/t/t_inst_wideconst.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -67,7 +67,3 @@ module wide (
    assign zzz = xxx+ { {40{1'b0}},yyy };
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v
index 7e5f0cac1..3e0557782 100644
--- a/test_regress/t/t_math_const.v
+++ b/test_regress/t/t_math_const.v
@@ -103,7 +103,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v
index e3b2681be..1bc3a603d 100644
--- a/test_regress/t/t_math_reverse.v
+++ b/test_regress/t/t_math_reverse.v
@@ -81,7 +81,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_math_tri.v b/test_regress/t/t_math_tri.v
index a98737793..ccfc259ba 100644
--- a/test_regress/t/t_math_tri.v
+++ b/test_regress/t/t_math_tri.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -20,7 +20,3 @@ module t (/*AUTOARG*/);
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v
index 7639244b2..64cc93159 100644
--- a/test_regress/t/t_mem.v
+++ b/test_regress/t/t_mem.v
@@ -66,7 +66,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v
index aa6e3fedd..157f356c9 100644
--- a/test_regress/t/t_order.v
+++ b/test_regress/t/t_order.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -106,7 +106,3 @@ module t (/*AUTOARG*/
    end
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_order_a.v b/test_regress/t/t_order_a.v
index 63ee364de..ac8d2e600 100644
--- a/test_regress/t/t_order_a.v
+++ b/test_regress/t/t_order_a.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -51,7 +51,3 @@ module t_order_a (/*AUTOARG*/
    wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_order_b.v b/test_regress/t/t_order_b.v
index 730e403a3..82733512f 100644
--- a/test_regress/t/t_order_b.v
+++ b/test_regress/t/t_order_b.v
@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -17,7 +17,3 @@ module t_order_b (/*AUTOARG*/
    wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r;
 
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/t_var_life.v b/test_regress/t/t_var_life.v
index e5cd45f10..e468b88d6 100644
--- a/test_regress/t/t_var_life.v
+++ b/test_regress/t/t_var_life.v
@@ -103,7 +103,3 @@ module t (/*AUTOARG*/
       end
    end
 endmodule
-
-// Local Variables:
-// compile-command: "./vlint __FILE__"
-// End:
diff --git a/test_regress/t/vlint b/test_regress/t/vlint
deleted file mode 100755
index 1ced22c17..000000000
--- a/test_regress/t/vlint
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-# $Id:$
-# DESCRIPTION: Verilator: Invoke linting
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-$DIRPROJECT_PREFIX/bin/vlint --brief \
-    +librescan +libext+.v -y . +incdir+../include \
-    --filt=STMINI,_NETNM,CWCCXX,CSYBEQ,CSEBEQ,NBAJAM,ITENST,STMFOR \
-    $*