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IEEE 1800-2012 is now the default language. This adds 4 new keywords and updates the svdpi.h and vpi_user.h header files.
This commit is contained in:
Wilson Snyder
parent
bb2822f4b5
commit
70fd64dcd6
3
Changes
3
Changes
@ -5,6 +5,9 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.846-devel
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** IEEE 1800-2012 is now the default language. This adds 4 new keywords
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and updates the svdpi.h and vpi_user.h header files.
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*** Add --report-unoptflat, bug611. [Jeremy Bennett]
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*** Add duplicate clock gate optimization, msg980. [Varun Koyyalagunta]
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@ -245,6 +245,7 @@ descriptions in the next sections for more information.
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+1364-2005ext+<ext> Use Verilog 2005 with file extension <ext>
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+1800-2005ext+<ext> Use SystemVerilog 2005 with file extension <ext>
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+1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
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+1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
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--assert Enable all assertions
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--autoflush Flush streams after all $displays
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--bbox-sys Blackbox unknown $system calls
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@ -314,7 +315,7 @@ descriptions in the next sections for more information.
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--sp Create SystemPerl output
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--stats Create statistics file
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-sv Enable SystemVerilog parsing
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+systemverilogext+<ext> Synonym for +1800-2009ext+<ext>
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+systemverilogext+<ext> Synonym for +1800-2012ext+<ext>
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--top-module <topname> Name of top level input module
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--trace Enable waveform creation
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--trace-depth <levels> Depth of tracing
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@ -374,6 +375,8 @@ with the --exe option.
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=item +1800-2009ext+I<ext>
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=item +1800-2012ext+I<ext>
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Specifies the language standard to be used with a specific filename
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extension, I<ext>.
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@ -585,7 +588,7 @@ C<--debug> is equivalent to C<--debugi 4>).
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Select the language to be used by default when first processing each
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Verilog file. The language value must be "1364-1995", "1364-2001",
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"1364-2005", "1800-2005" or "1800-2009".
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"1364-2005", "1800-2005", "1800-2009" or "1800-2012".
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Any language associated with a particular file extension (see the various
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+I<lang>ext+ options) will be used in preference to the language specified
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@ -598,7 +601,7 @@ legacy mixed language designs, the various +I<lang>ext+ options should be
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used.
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If no language is specified, either by this flag or +I<lang>ext+ options,
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then the latest SystemVerilog language (IEEE 1800-2009) is used.
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then the latest SystemVerilog language (IEEE 1800-2012) is used.
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=item +define+I<var>+I<value>
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@ -940,7 +943,7 @@ compatibility with other simulators.
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=item +systemverilogext+I<ext>
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A synonym for C<+1800-2009ext+>I<ext>.
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A synonym for C<+1800-2012ext+>I<ext>.
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=item --top-module I<topname>
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@ -1916,13 +1919,13 @@ It also supports .name and .* interconnection.
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Verilator partially supports concurrent assert and cover statements; see
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the enclosed coverage tests for the syntax which is allowed.
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=head2 SystemVerilog 2009 (IEEE 1800-2009) Support
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=head2 SystemVerilog 2012 (IEEE 1800-2012) Support
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Verilator implements a full SystemVerilog 2009 preprocessor, including
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Verilator implements a full SystemVerilog 2012 preprocessor, including
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function call-like preprocessor defines, default define arguments,
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`__FILE__, `__LINE__ and `undefineall.
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Verilator currently has some support for SystemVerilog 2009 synthesis
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Verilator currently has some support for SystemVerilog synthesis
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constructs. As SystemVerilog features enter common usage they are added;
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please file a bug if a feature you need is missing.
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@ -7,7 +7,7 @@
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* This file contains the constant definitions, structure definitions,
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* and routine declarations used by SystemVerilog DPI.
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*
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* This file is from the SystemVerilog IEEE 1800-2009 Annex I.
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* This file is from the SystemVerilog IEEE 1800-2012 Annex I.
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*/
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#ifndef INCLUDED_SVDPI
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@ -35,18 +35,18 @@ typedef signed __int8 int8_t;
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#include <sys/types.h>
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#endif
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/* Use to export a symbol from application */
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/* Use to import a symbol into dll */
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#ifndef DPI_DLLISPEC
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#if defined (_MSC_VER)
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#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__))
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#define DPI_DLLISPEC __declspec(dllimport)
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#else
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#define DPI_DLLISPEC
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#endif
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#endif
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/* Use to import a symbol into application */
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/* Use to export a symbol from dll */
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#ifndef DPI_DLLESPEC
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#if defined (_MSC_VER)
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#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__))
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#define DPI_DLLESPEC __declspec(dllexport)
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#else
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#define DPI_DLLESPEC
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@ -1,7 +1,7 @@
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/*******************************************************************************
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* vpi_user.h
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*
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* IEEE Std 1800 Programming Language Interface (PLI)
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* IEEE Std 1800-2012 Programming Language Interface (PLI)
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*
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* This file contains the constant definitions, structure definitions, and
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* routine declarations used by the SystemVerilog Verification Procedural
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@ -61,9 +61,9 @@ typedef char PLI_BYTE8;
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typedef unsigned char PLI_UBYTE8;
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#endif
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/* Use to export a symbol */
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/* Use to import a symbol */
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#if WIN32
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#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__))
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#ifndef PLI_DLLISPEC
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#define PLI_DLLISPEC __declspec(dllimport)
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#define VPI_USER_DEFINED_DLLISPEC 1
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@ -74,9 +74,9 @@ typedef unsigned char PLI_UBYTE8;
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#endif
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#endif
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/* Use to import a symbol */
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/* Use to export a symbol */
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#if WIN32
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#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__))
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#ifndef PLI_DLLESPEC
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#define PLI_DLLESPEC __declspec(dllexport)
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#define VPI_USER_DEFINED_DLLESPEC 1
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@ -438,12 +438,12 @@ typedef PLI_UINT32 *vpiHandle;
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#define vpiPlusOp 2 /* unary plus */
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#define vpiNotOp 3 /* unary not */
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#define vpiBitNegOp 4 /* bitwise negation */
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#define vpiUnaryAndOp 5 /* bitwise reduction and */
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#define vpiUnaryNandOp 6 /* bitwise reduction nand */
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#define vpiUnaryOrOp 7 /* bitwise reduction or */
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#define vpiUnaryNorOp 8 /* bitwise reduction nor */
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#define vpiUnaryXorOp 9 /* bitwise reduction xor */
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#define vpiUnaryXNorOp 10 /* bitwise reduction xnor */
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#define vpiUnaryAndOp 5 /* bitwise reduction AND */
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#define vpiUnaryNandOp 6 /* bitwise reduction NAND */
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#define vpiUnaryOrOp 7 /* bitwise reduction OR */
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#define vpiUnaryNorOp 8 /* bitwise reduction NOR */
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#define vpiUnaryXorOp 9 /* bitwise reduction XOR */
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#define vpiUnaryXNorOp 10 /* bitwise reduction XNOR */
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#define vpiSubOp 11 /* binary subtraction */
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#define vpiDivOp 12 /* binary division */
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#define vpiModOp 13 /* binary modulus */
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@ -459,17 +459,17 @@ typedef PLI_UINT32 *vpiHandle;
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#define vpiRShiftOp 23 /* binary right shift */
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#define vpiAddOp 24 /* binary addition */
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#define vpiMultOp 25 /* binary multiplication */
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#define vpiLogAndOp 26 /* binary logical and */
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#define vpiLogOrOp 27 /* binary logical or */
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#define vpiBitAndOp 28 /* binary bitwise and */
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#define vpiBitOrOp 29 /* binary bitwise or */
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#define vpiBitXorOp 30 /* binary bitwise xor */
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#define vpiBitXNorOp 31 /* binary bitwise xnor */
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#define vpiLogAndOp 26 /* binary logical AND */
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#define vpiLogOrOp 27 /* binary logical OR */
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#define vpiBitAndOp 28 /* binary bitwise AND */
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#define vpiBitOrOp 29 /* binary bitwise OR */
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#define vpiBitXorOp 30 /* binary bitwise XOR */
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#define vpiBitXNorOp 31 /* binary bitwise XNOR */
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#define vpiBitXnorOp vpiBitXNorOp /* added with 1364-2001 */
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#define vpiConditionOp 32 /* ternary conditional */
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#define vpiConcatOp 33 /* n-ary concatenation */
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#define vpiMultiConcatOp 34 /* repeated concatenation */
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#define vpiEventOrOp 35 /* event or */
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#define vpiEventOrOp 35 /* event OR */
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#define vpiNullOp 36 /* null operation */
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#define vpiListOp 37 /* list of expressions */
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#define vpiMinTypMaxOp 38 /* min:typ:max: delay expression */
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@ -536,7 +536,7 @@ typedef PLI_UINT32 *vpiHandle;
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same subtypes as vpiNetType */
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#define vpiSaveRestartID 62 /* unique ID for save/restart data */
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#define vpiSaveRestartLocation 63 /* name of save/restart data file */
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/* vpiValid,vpiValidTrue,vpiValidFalse are deprecated in 1800-2009 */
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/* vpiValid,vpiValidTrue,vpiValidFalse were deprecated in 1800-2009 */
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#define vpiValid 64 /* reentrant task/func frame or automatic
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variable is valid */
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#define vpiValidFalse 0
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@ -661,7 +661,7 @@ typedef struct t_vpi_arrayvalue
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{
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PLI_INT32 *integers; /* integer values */
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PLI_INT16 *shortints; /* short integer values */
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PLI_INT16 *longints; /* long integer values */
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PLI_INT64 *longints; /* long integer values */
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PLI_BYTE8 *rawvals; /* 2/4-state vector elements */
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struct t_vpi_vecval *vectors; /* 4-state vector elements */
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struct t_vpi_time *times; /* time values */
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@ -944,7 +944,7 @@ XXTERN PLI_INT32 vpi_compare_objects PROTO_PARAMS((vpiHandle object1,
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vpiHandle object2));
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XXTERN PLI_INT32 vpi_chk_error PROTO_PARAMS((p_vpi_error_info
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error_info_p));
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/* vpi_free_object() is deprecated in 1800-2009 */
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/* vpi_free_object() was deprecated in 1800-2009 */
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XXTERN PLI_INT32 vpi_free_object PROTO_PARAMS((vpiHandle object));
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XXTERN PLI_INT32 vpi_release_handle PROTO_PARAMS((vpiHandle object));
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XXTERN PLI_INT32 vpi_get_vlog_info PROTO_PARAMS((p_vpi_vlog_info
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@ -41,6 +41,7 @@ public:
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L1364_2005,
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L1800_2005,
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L1800_2009,
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L1800_2012,
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// ***Add new elements below also***
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_ENUM_END
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};
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@ -52,12 +53,13 @@ public:
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"1364-2001",
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"1364-2005",
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"1800-2005",
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"1800-2009"
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"1800-2009",
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"1800-2012"
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};
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return names[m_e];
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};
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static V3LangCode mostRecent() { return V3LangCode(L1800_2009); }
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bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009; }
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static V3LangCode mostRecent() { return V3LangCode(L1800_2012); }
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bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012; }
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bool legal() const { return m_e != L_ERROR; }
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//
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enum en m_e;
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@ -673,14 +673,15 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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else if ( !strncmp (sw, "+incdir+", 8)) {
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addIncDirUser (parseFileArg(optdir, string (sw+strlen("+incdir+"))));
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}
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else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2009)
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else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2012)
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|| parseLangExt(sw, "+verilog1995ext+", V3LangCode::L1364_1995)
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|| parseLangExt(sw, "+verilog2001ext+", V3LangCode::L1364_2001)
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|| parseLangExt(sw, "+1364-1995ext+", V3LangCode::L1364_1995)
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|| parseLangExt(sw, "+1364-2001ext+", V3LangCode::L1364_2001)
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|| parseLangExt(sw, "+1364-2005ext+", V3LangCode::L1364_2005)
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|| parseLangExt(sw, "+1800-2005ext+", V3LangCode::L1800_2005)
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|| parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009)) {
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|| parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009)
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|| parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012)) {
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// Nothing to do here - all done in the test
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}
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@ -32,7 +32,7 @@
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extern void yyerror(const char*);
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extern void yyerrorf(const char* format, ...);
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#define STATE_VERILOG_RECENT S09 // State name for most recent Verilog Version
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#define STATE_VERILOG_RECENT S12 // State name for most recent Verilog Version
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#define PARSEP V3ParseImp::parsep()
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#define SYMP PARSEP->symp()
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@ -135,7 +135,7 @@ void yyerrorf(const char* format, ...) {
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%a 15000
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%o 25000
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%s V95 V01 V05 S05 S09
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%s V95 V01 V05 S05 S09 S12
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%s STRING ATTRMODE TABLE
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%s VA5 SA9 PSL VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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@ -171,7 +171,7 @@ word [a-zA-Z0-9_]+
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,VA5,S05,S09,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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{ws} { } /* otherwise ignore white-space */
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{crnl} { NEXTLINE(); } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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@ -344,7 +344,7 @@ word [a-zA-Z0-9_]+
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}
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/* Verilog 2001 */
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<V01,V05,VA5,S05,S09,SA9,PSL>{
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<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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/* System Tasks */
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"$signed" { FL; return yD_SIGNED; }
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"$unsigned" { FL; return yD_UNSIGNED; }
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@ -375,13 +375,13 @@ word [a-zA-Z0-9_]+
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}
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/* Verilog 2005 */
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<V05,S05,S09,SA9,PSL>{
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<V05,S05,S09,S12,SA9,PSL>{
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/* Keywords */
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"uwire" { FL; return yWIRE; }
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}
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/* System Verilog 2005 */
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<S05,S09,PSL>{
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<S05,S09,S12,PSL>{
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/* System Tasks */
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"$bits" { FL; return yD_BITS; }
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"$clog2" { FL; return yD_CLOG2; }
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@ -498,7 +498,7 @@ word [a-zA-Z0-9_]+
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}
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/* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */
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<S05,S09>{
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<S05,S09,S12>{
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/* Keywords */
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"assert" { FL; return yASSERT; }
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"const" { FL; return yCONST__LEX; }
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@ -513,7 +513,7 @@ word [a-zA-Z0-9_]+
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}
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/* SystemVerilog 2009 */
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<S09,PSL>{
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<S09,S12,PSL>{
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/* Keywords */
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"global" { FL; return yGLOBAL__LEX; }
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"unique0" { FL; return yUNIQUE0; }
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@ -541,8 +541,17 @@ word [a-zA-Z0-9_]+
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"weak" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
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}
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/* System Verilog 2012 */
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<S12,PSL>{
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/* Keywords */
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"implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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"interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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"nettype" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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"soft" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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}
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/* Default PLI rule */
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<V95,V01,V05,VA5,S05,S09,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng);
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yylval.strp = PARSEP->newString(AstNode::encodeName(str));
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// Lookup unencoded name including the $, to avoid hitting normal signals
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@ -649,7 +658,7 @@ word [a-zA-Z0-9_]+
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/* PSL */
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/*Entry into PSL; mode change */
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<V95,V01,V05,VA5,S05,S09,SA9>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9>{
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"psl" { yy_push_state(PSL); FL; return yPSL; }
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}
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@ -738,7 +747,7 @@ word [a-zA-Z0-9_]+
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/* Meta comments */
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/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
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<V95,V01,V05,VA5,S05,S09,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
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"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
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"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
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@ -773,11 +782,11 @@ word [a-zA-Z0-9_]+
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/************************************************************************/
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/* Single character operator thingies */
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<V95,V01,V05,VA5,S05,S09,SA9>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9>{
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"{" { FL; return yytext[0]; }
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"}" { FL; return yytext[0]; }
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}
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<V95,V01,V05,VA5,S05,S09,SA9,PSL>{
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<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
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"!" { FL; return yytext[0]; }
|
||||
"#" { FL; return yytext[0]; }
|
||||
"$" { FL; return yytext[0]; }
|
||||
@ -809,7 +818,7 @@ word [a-zA-Z0-9_]+
|
||||
/* Operators and multi-character symbols */
|
||||
|
||||
/* Verilog 1995 Operators */
|
||||
<V95,V01,V05,VA5,S05,S09,SA9,PSL>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL>{
|
||||
"&&" { FL; return yP_ANDAND; }
|
||||
"||" { FL; return yP_OROR; }
|
||||
"<=" { FL; return yP_LTE; }
|
||||
@ -831,7 +840,7 @@ word [a-zA-Z0-9_]+
|
||||
}
|
||||
|
||||
/* Verilog 2001 Operators */
|
||||
<V01,V05,VA5,S05,S09,SA9,PSL>{
|
||||
<V01,V05,VA5,S05,S09,S12,SA9,PSL>{
|
||||
"<<<" { FL; return yP_SLEFT; }
|
||||
">>>" { FL; return yP_SSRIGHT; }
|
||||
"**" { FL; return yP_POW; }
|
||||
@ -841,7 +850,7 @@ word [a-zA-Z0-9_]+
|
||||
}
|
||||
|
||||
/* SystemVerilog Operators */
|
||||
<S05,S09>{
|
||||
<S05,S09,S12>{
|
||||
"'" { FL; return yP_TICK; }
|
||||
"'{" { FL; return yP_TICKBRA; }
|
||||
"==?" { FL; return yP_WILDEQUAL; }
|
||||
@ -890,7 +899,7 @@ word [a-zA-Z0-9_]+
|
||||
}
|
||||
|
||||
/* Identifiers and numbers */
|
||||
<V95,V01,V05,VA5,S05,S09,SA9,PSL,VLT>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
|
||||
{escid} { FL; yylval.strp = PARSEP->newString
|
||||
(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
|
||||
return yaID__LEX;
|
||||
@ -966,7 +975,7 @@ word [a-zA-Z0-9_]+
|
||||
/************************************************************************/
|
||||
/* Attributes */
|
||||
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
|
||||
<V95,V01,V05,VA5,S05,S09,SA9>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SA9>{
|
||||
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec
|
||||
}
|
||||
|
||||
@ -983,7 +992,7 @@ word [a-zA-Z0-9_]+
|
||||
/* Preprocessor */
|
||||
/* Common for all SYSC header states */
|
||||
/* OPTIMIZE: we return one per line, make it one for the entire block */
|
||||
<V95,V01,V05,VA5,S05,S09,SA9,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
||||
"`accelerate" { } // Verilog-XL compatibility
|
||||
"`autoexpand_vectornets" { } // Verilog-XL compatibility
|
||||
"`celldefine" { PARSEP->inCellDefine(true); }
|
||||
@ -1027,6 +1036,7 @@ word [a-zA-Z0-9_]+
|
||||
"`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { yy_push_state(VA5); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800+VAMS\" { yy_push_state(SA9); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
|
||||
|
||||
@ -1058,7 +1068,7 @@ word [a-zA-Z0-9_]+
|
||||
/************************************************************************/
|
||||
/* Default rules - leave last */
|
||||
|
||||
<V95,V01,V05,VA5,S05,S09,SA9,PSL,VLT>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SA9,PSL,VLT>{
|
||||
"`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); }
|
||||
"//"[^\n]* { } /* throw away single line comments */
|
||||
. { FL; return yytext[0]; } /* return single char ops. */
|
||||
|
||||
@ -9,12 +9,13 @@ module t (/*AUTOARG*/
|
||||
);
|
||||
input clk;
|
||||
|
||||
s1 s1 ();
|
||||
s2 s2 ();
|
||||
s3 s3 ();
|
||||
s4 s4 ();
|
||||
s5 s5 ();
|
||||
s6 s6 ();
|
||||
v95 v95 ();
|
||||
v01 v01 ();
|
||||
v05 v05 ();
|
||||
s05 s05 ();
|
||||
s09 s09 ();
|
||||
a23 a23 ();
|
||||
s12 s12 ();
|
||||
|
||||
initial begin
|
||||
$finish;
|
||||
@ -22,31 +23,37 @@ module t (/*AUTOARG*/
|
||||
endmodule
|
||||
|
||||
`begin_keywords "1364-1995"
|
||||
module s1;
|
||||
module v95;
|
||||
integer signed; initial signed = 1;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1364-2001"
|
||||
module s2;
|
||||
module v01;
|
||||
integer bit; initial bit = 1;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1364-2005"
|
||||
module s3;
|
||||
module v05;
|
||||
integer final; initial final = 1;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1800-2005"
|
||||
module s4;
|
||||
module s05;
|
||||
integer global; initial global = 1;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1800-2009"
|
||||
module s5;
|
||||
module s09;
|
||||
integer soft; initial soft = 1;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1800-2012"
|
||||
module s12;
|
||||
final begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
end
|
||||
@ -54,7 +61,7 @@ endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "VAMS-2.3"
|
||||
module s6;
|
||||
module a23;
|
||||
real foo; initial foo = sqrt(2.0);
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
Loading…
Reference in New Issue
Block a user