diff --git a/Changes b/Changes index 350478b8f..05f0412fb 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,9 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.846-devel +** IEEE 1800-2012 is now the default language. This adds 4 new keywords + and updates the svdpi.h and vpi_user.h header files. + *** Add --report-unoptflat, bug611. [Jeremy Bennett] *** Add duplicate clock gate optimization, msg980. [Varun Koyyalagunta] diff --git a/bin/verilator b/bin/verilator index 6c11a0a11..2a777edbc 100755 --- a/bin/verilator +++ b/bin/verilator @@ -245,6 +245,7 @@ descriptions in the next sections for more information. +1364-2005ext+ Use Verilog 2005 with file extension +1800-2005ext+ Use SystemVerilog 2005 with file extension +1800-2009ext+ Use SystemVerilog 2009 with file extension + +1800-2012ext+ Use SystemVerilog 2012 with file extension --assert Enable all assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls @@ -314,7 +315,7 @@ descriptions in the next sections for more information. --sp Create SystemPerl output --stats Create statistics file -sv Enable SystemVerilog parsing - +systemverilogext+ Synonym for +1800-2009ext+ + +systemverilogext+ Synonym for +1800-2012ext+ --top-module Name of top level input module --trace Enable waveform creation --trace-depth Depth of tracing @@ -374,6 +375,8 @@ with the --exe option. =item +1800-2009ext+I +=item +1800-2012ext+I + Specifies the language standard to be used with a specific filename extension, I. @@ -585,7 +588,7 @@ C<--debug> is equivalent to C<--debugi 4>). Select the language to be used by default when first processing each Verilog file. The language value must be "1364-1995", "1364-2001", -"1364-2005", "1800-2005" or "1800-2009". +"1364-2005", "1800-2005", "1800-2009" or "1800-2012". Any language associated with a particular file extension (see the various +Iext+ options) will be used in preference to the language specified @@ -598,7 +601,7 @@ legacy mixed language designs, the various +Iext+ options should be used. If no language is specified, either by this flag or +Iext+ options, -then the latest SystemVerilog language (IEEE 1800-2009) is used. +then the latest SystemVerilog language (IEEE 1800-2012) is used. =item +define+I+I @@ -940,7 +943,7 @@ compatibility with other simulators. =item +systemverilogext+I -A synonym for C<+1800-2009ext+>I. +A synonym for C<+1800-2012ext+>I. =item --top-module I @@ -1916,13 +1919,13 @@ It also supports .name and .* interconnection. Verilator partially supports concurrent assert and cover statements; see the enclosed coverage tests for the syntax which is allowed. -=head2 SystemVerilog 2009 (IEEE 1800-2009) Support +=head2 SystemVerilog 2012 (IEEE 1800-2012) Support -Verilator implements a full SystemVerilog 2009 preprocessor, including +Verilator implements a full SystemVerilog 2012 preprocessor, including function call-like preprocessor defines, default define arguments, `__FILE__, `__LINE__ and `undefineall. -Verilator currently has some support for SystemVerilog 2009 synthesis +Verilator currently has some support for SystemVerilog synthesis constructs. As SystemVerilog features enter common usage they are added; please file a bug if a feature you need is missing. diff --git a/include/vltstd/svdpi.h b/include/vltstd/svdpi.h index 4a8af229f..3e601933e 100644 --- a/include/vltstd/svdpi.h +++ b/include/vltstd/svdpi.h @@ -7,7 +7,7 @@ * This file contains the constant definitions, structure definitions, * and routine declarations used by SystemVerilog DPI. * - * This file is from the SystemVerilog IEEE 1800-2009 Annex I. + * This file is from the SystemVerilog IEEE 1800-2012 Annex I. */ #ifndef INCLUDED_SVDPI @@ -35,18 +35,18 @@ typedef signed __int8 int8_t; #include #endif -/* Use to export a symbol from application */ +/* Use to import a symbol into dll */ #ifndef DPI_DLLISPEC -#if defined (_MSC_VER) +#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #define DPI_DLLISPEC __declspec(dllimport) #else #define DPI_DLLISPEC #endif #endif -/* Use to import a symbol into application */ +/* Use to export a symbol from dll */ #ifndef DPI_DLLESPEC -#if defined (_MSC_VER) +#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #define DPI_DLLESPEC __declspec(dllexport) #else #define DPI_DLLESPEC diff --git a/include/vltstd/vpi_user.h b/include/vltstd/vpi_user.h index a2c11a01a..4d5fc1575 100644 --- a/include/vltstd/vpi_user.h +++ b/include/vltstd/vpi_user.h @@ -1,7 +1,7 @@ /******************************************************************************* * vpi_user.h * - * IEEE Std 1800 Programming Language Interface (PLI) + * IEEE Std 1800-2012 Programming Language Interface (PLI) * * This file contains the constant definitions, structure definitions, and * routine declarations used by the SystemVerilog Verification Procedural @@ -61,9 +61,9 @@ typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif -/* Use to export a symbol */ +/* Use to import a symbol */ -#if WIN32 +#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #ifndef PLI_DLLISPEC #define PLI_DLLISPEC __declspec(dllimport) #define VPI_USER_DEFINED_DLLISPEC 1 @@ -74,9 +74,9 @@ typedef unsigned char PLI_UBYTE8; #endif #endif -/* Use to import a symbol */ +/* Use to export a symbol */ -#if WIN32 +#if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #ifndef PLI_DLLESPEC #define PLI_DLLESPEC __declspec(dllexport) #define VPI_USER_DEFINED_DLLESPEC 1 @@ -438,12 +438,12 @@ typedef PLI_UINT32 *vpiHandle; #define vpiPlusOp 2 /* unary plus */ #define vpiNotOp 3 /* unary not */ #define vpiBitNegOp 4 /* bitwise negation */ -#define vpiUnaryAndOp 5 /* bitwise reduction and */ -#define vpiUnaryNandOp 6 /* bitwise reduction nand */ -#define vpiUnaryOrOp 7 /* bitwise reduction or */ -#define vpiUnaryNorOp 8 /* bitwise reduction nor */ -#define vpiUnaryXorOp 9 /* bitwise reduction xor */ -#define vpiUnaryXNorOp 10 /* bitwise reduction xnor */ +#define vpiUnaryAndOp 5 /* bitwise reduction AND */ +#define vpiUnaryNandOp 6 /* bitwise reduction NAND */ +#define vpiUnaryOrOp 7 /* bitwise reduction OR */ +#define vpiUnaryNorOp 8 /* bitwise reduction NOR */ +#define vpiUnaryXorOp 9 /* bitwise reduction XOR */ +#define vpiUnaryXNorOp 10 /* bitwise reduction XNOR */ #define vpiSubOp 11 /* binary subtraction */ #define vpiDivOp 12 /* binary division */ #define vpiModOp 13 /* binary modulus */ @@ -459,17 +459,17 @@ typedef PLI_UINT32 *vpiHandle; #define vpiRShiftOp 23 /* binary right shift */ #define vpiAddOp 24 /* binary addition */ #define vpiMultOp 25 /* binary multiplication */ -#define vpiLogAndOp 26 /* binary logical and */ -#define vpiLogOrOp 27 /* binary logical or */ -#define vpiBitAndOp 28 /* binary bitwise and */ -#define vpiBitOrOp 29 /* binary bitwise or */ -#define vpiBitXorOp 30 /* binary bitwise xor */ -#define vpiBitXNorOp 31 /* binary bitwise xnor */ +#define vpiLogAndOp 26 /* binary logical AND */ +#define vpiLogOrOp 27 /* binary logical OR */ +#define vpiBitAndOp 28 /* binary bitwise AND */ +#define vpiBitOrOp 29 /* binary bitwise OR */ +#define vpiBitXorOp 30 /* binary bitwise XOR */ +#define vpiBitXNorOp 31 /* binary bitwise XNOR */ #define vpiBitXnorOp vpiBitXNorOp /* added with 1364-2001 */ #define vpiConditionOp 32 /* ternary conditional */ #define vpiConcatOp 33 /* n-ary concatenation */ #define vpiMultiConcatOp 34 /* repeated concatenation */ -#define vpiEventOrOp 35 /* event or */ +#define vpiEventOrOp 35 /* event OR */ #define vpiNullOp 36 /* null operation */ #define vpiListOp 37 /* list of expressions */ #define vpiMinTypMaxOp 38 /* min:typ:max: delay expression */ @@ -536,7 +536,7 @@ typedef PLI_UINT32 *vpiHandle; same subtypes as vpiNetType */ #define vpiSaveRestartID 62 /* unique ID for save/restart data */ #define vpiSaveRestartLocation 63 /* name of save/restart data file */ -/* vpiValid,vpiValidTrue,vpiValidFalse are deprecated in 1800-2009 */ +/* vpiValid,vpiValidTrue,vpiValidFalse were deprecated in 1800-2009 */ #define vpiValid 64 /* reentrant task/func frame or automatic variable is valid */ #define vpiValidFalse 0 @@ -661,7 +661,7 @@ typedef struct t_vpi_arrayvalue { PLI_INT32 *integers; /* integer values */ PLI_INT16 *shortints; /* short integer values */ - PLI_INT16 *longints; /* long integer values */ + PLI_INT64 *longints; /* long integer values */ PLI_BYTE8 *rawvals; /* 2/4-state vector elements */ struct t_vpi_vecval *vectors; /* 4-state vector elements */ struct t_vpi_time *times; /* time values */ @@ -944,7 +944,7 @@ XXTERN PLI_INT32 vpi_compare_objects PROTO_PARAMS((vpiHandle object1, vpiHandle object2)); XXTERN PLI_INT32 vpi_chk_error PROTO_PARAMS((p_vpi_error_info error_info_p)); -/* vpi_free_object() is deprecated in 1800-2009 */ +/* vpi_free_object() was deprecated in 1800-2009 */ XXTERN PLI_INT32 vpi_free_object PROTO_PARAMS((vpiHandle object)); XXTERN PLI_INT32 vpi_release_handle PROTO_PARAMS((vpiHandle object)); XXTERN PLI_INT32 vpi_get_vlog_info PROTO_PARAMS((p_vpi_vlog_info diff --git a/src/V3LangCode.h b/src/V3LangCode.h index 91eb32719..94bf48837 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -41,6 +41,7 @@ public: L1364_2005, L1800_2005, L1800_2009, + L1800_2012, // ***Add new elements below also*** _ENUM_END }; @@ -52,12 +53,13 @@ public: "1364-2001", "1364-2005", "1800-2005", - "1800-2009" + "1800-2009", + "1800-2012" }; return names[m_e]; }; - static V3LangCode mostRecent() { return V3LangCode(L1800_2009); } - bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009; } + static V3LangCode mostRecent() { return V3LangCode(L1800_2012); } + bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012; } bool legal() const { return m_e != L_ERROR; } // enum en m_e; diff --git a/src/V3Options.cpp b/src/V3Options.cpp index db3f43f70..abb6b57f0 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -673,14 +673,15 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char else if ( !strncmp (sw, "+incdir+", 8)) { addIncDirUser (parseFileArg(optdir, string (sw+strlen("+incdir+")))); } - else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2009) + else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2012) || parseLangExt(sw, "+verilog1995ext+", V3LangCode::L1364_1995) || parseLangExt(sw, "+verilog2001ext+", V3LangCode::L1364_2001) || parseLangExt(sw, "+1364-1995ext+", V3LangCode::L1364_1995) || parseLangExt(sw, "+1364-2001ext+", V3LangCode::L1364_2001) || parseLangExt(sw, "+1364-2005ext+", V3LangCode::L1364_2005) || parseLangExt(sw, "+1800-2005ext+", V3LangCode::L1800_2005) - || parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009)) { + || parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009) + || parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012)) { // Nothing to do here - all done in the test } diff --git a/src/verilog.l b/src/verilog.l index 1a6e206a3..7fe5a643f 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -32,7 +32,7 @@ extern void yyerror(const char*); extern void yyerrorf(const char* format, ...); -#define STATE_VERILOG_RECENT S09 // State name for most recent Verilog Version +#define STATE_VERILOG_RECENT S12 // State name for most recent Verilog Version #define PARSEP V3ParseImp::parsep() #define SYMP PARSEP->symp() @@ -135,7 +135,7 @@ void yyerrorf(const char* format, ...) { %a 15000 %o 25000 -%s V95 V01 V05 S05 S09 +%s V95 V01 V05 S05 S09 S12 %s STRING ATTRMODE TABLE %s VA5 SA9 PSL VLT %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR @@ -171,7 +171,7 @@ word [a-zA-Z0-9_]+ /************************************************************************/ /* Verilog 1995 */ -{ +{ {ws} { } /* otherwise ignore white-space */ {crnl} { NEXTLINE(); } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ @@ -344,7 +344,7 @@ word [a-zA-Z0-9_]+ } /* Verilog 2001 */ -{ +{ /* System Tasks */ "$signed" { FL; return yD_SIGNED; } "$unsigned" { FL; return yD_UNSIGNED; } @@ -375,13 +375,13 @@ word [a-zA-Z0-9_]+ } /* Verilog 2005 */ -{ +{ /* Keywords */ "uwire" { FL; return yWIRE; } } /* System Verilog 2005 */ -{ +{ /* System Tasks */ "$bits" { FL; return yD_BITS; } "$clog2" { FL; return yD_CLOG2; } @@ -498,7 +498,7 @@ word [a-zA-Z0-9_]+ } /* SystemVerilog 2005 ONLY not PSL; different rules for PSL as specified below */ -{ +{ /* Keywords */ "assert" { FL; return yASSERT; } "const" { FL; return yCONST__LEX; } @@ -513,7 +513,7 @@ word [a-zA-Z0-9_]+ } /* SystemVerilog 2009 */ -{ +{ /* Keywords */ "global" { FL; return yGLOBAL__LEX; } "unique0" { FL; return yUNIQUE0; } @@ -541,8 +541,17 @@ word [a-zA-Z0-9_]+ "weak" { yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); } } + /* System Verilog 2012 */ +{ + /* Keywords */ + "implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } + "interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } + "nettype" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } + "soft" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); } +} + /* Default PLI rule */ -{ +{ "$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng); yylval.strp = PARSEP->newString(AstNode::encodeName(str)); // Lookup unencoded name including the $, to avoid hitting normal signals @@ -649,7 +658,7 @@ word [a-zA-Z0-9_]+ /* PSL */ /*Entry into PSL; mode change */ -{ +{ "psl" { yy_push_state(PSL); FL; return yPSL; } } @@ -738,7 +747,7 @@ word [a-zA-Z0-9_]+ /* Meta comments */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ -{ +{ "/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } @@ -773,11 +782,11 @@ word [a-zA-Z0-9_]+ /************************************************************************/ /* Single character operator thingies */ -{ +{ "{" { FL; return yytext[0]; } "}" { FL; return yytext[0]; } } -{ +{ "!" { FL; return yytext[0]; } "#" { FL; return yytext[0]; } "$" { FL; return yytext[0]; } @@ -809,7 +818,7 @@ word [a-zA-Z0-9_]+ /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ -{ +{ "&&" { FL; return yP_ANDAND; } "||" { FL; return yP_OROR; } "<=" { FL; return yP_LTE; } @@ -831,7 +840,7 @@ word [a-zA-Z0-9_]+ } /* Verilog 2001 Operators */ -{ +{ "<<<" { FL; return yP_SLEFT; } ">>>" { FL; return yP_SSRIGHT; } "**" { FL; return yP_POW; } @@ -841,7 +850,7 @@ word [a-zA-Z0-9_]+ } /* SystemVerilog Operators */ -{ +{ "'" { FL; return yP_TICK; } "'{" { FL; return yP_TICKBRA; } "==?" { FL; return yP_WILDEQUAL; } @@ -890,7 +899,7 @@ word [a-zA-Z0-9_]+ } /* Identifiers and numbers */ -{ +{ {escid} { FL; yylval.strp = PARSEP->newString (AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash return yaID__LEX; @@ -966,7 +975,7 @@ word [a-zA-Z0-9_]+ /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ -{ +{ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec } @@ -983,7 +992,7 @@ word [a-zA-Z0-9_]+ /* Preprocessor */ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ -{ +{ "`accelerate" { } // Verilog-XL compatibility "`autoexpand_vectornets" { } // Verilog-XL compatibility "`celldefine" { PARSEP->inCellDefine(true); } @@ -1027,6 +1036,7 @@ word [a-zA-Z0-9_]+ "`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { yy_push_state(VA5); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); } "`begin_keywords"[ \t]*\"1800+VAMS\" { yy_push_state(SA9); PARSEP->pushBeginKeywords(YY_START); } "`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } @@ -1058,7 +1068,7 @@ word [a-zA-Z0-9_]+ /************************************************************************/ /* Default rules - leave last */ -{ +{ "`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); } "//"[^\n]* { } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index 26f7fff30..85fb878e1 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -9,12 +9,13 @@ module t (/*AUTOARG*/ ); input clk; - s1 s1 (); - s2 s2 (); - s3 s3 (); - s4 s4 (); - s5 s5 (); - s6 s6 (); + v95 v95 (); + v01 v01 (); + v05 v05 (); + s05 s05 (); + s09 s09 (); + a23 a23 (); + s12 s12 (); initial begin $finish; @@ -22,31 +23,37 @@ module t (/*AUTOARG*/ endmodule `begin_keywords "1364-1995" -module s1; +module v95; integer signed; initial signed = 1; endmodule `end_keywords `begin_keywords "1364-2001" -module s2; +module v01; integer bit; initial bit = 1; endmodule `end_keywords `begin_keywords "1364-2005" -module s3; +module v05; integer final; initial final = 1; endmodule `end_keywords `begin_keywords "1800-2005" -module s4; +module s05; integer global; initial global = 1; endmodule `end_keywords `begin_keywords "1800-2009" -module s5; +module s09; + integer soft; initial soft = 1; +endmodule +`end_keywords + +`begin_keywords "1800-2012" +module s12; final begin $write("*-* All Finished *-*\n"); end @@ -54,7 +61,7 @@ endmodule `end_keywords `begin_keywords "VAMS-2.3" -module s6; +module a23; real foo; initial foo = sqrt(2.0); endmodule `end_keywords