Fix arrayed instances

git-svn-id: file://localhost/svn/verilator/trunk/verilator@774 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -14,9 +14,11 @@ indicates the contributor was also the author of the fix; Thanks!
 ***  Changed how internal functions are invoked to reduce aliasing.
      Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%.
 
+**** Fix memory leak when destroying modules.  [John Stroebel]
+
 **** Fix coredump when unused modules have unused cells.  [David Hewson]
 
-**** Fix memory leak when destroying modules.  [John Stroebel]
+**** Fix 3.600 internal error with arrayed instances.  [David Hewson]
 
 **** Fix $display %m name not matching Verilog name inside SystemC modules.
 

bin/verilator

@@ -1115,8 +1115,8 @@ always @* to prevent these issues.)
 =head2 Dotted cross-hierarchy references
 
 Verilator supports dotted references to variables, functions and tasks in
-different modules. However, references into named blocks and function-local
-variables are not supported.
+different modules. However, references into named blocks, function-local
+variables, and arrayed instances are not supported.
 
 =head2 Latches
 

src/V3AstNodes.h

@@ -650,17 +650,18 @@ public:
     virtual bool broken() const { return (m_modp && !m_modp->brokeExists()); }
     // ACCESSORS
     virtual string name()	const { return m_name; }		// * = Cell name
+    void name(const string& name) 	{ m_name = name; }
     string origName()		const { return m_origName; }		// * = Original name
+    void origName(const string& name) 	{ m_origName = name; }
     string modName()		const { return m_modName; }		// * = Instance name
+    void modName(const string& name)	{ m_modName = name; }
     AstPin* pinsp()		const { return op1p()->castPin(); }	// op1 = List of cell ports
     AstPin* paramsp()		const { return op2p()->castPin(); }	// op2 = List of parameter #(##) values
     AstRange* rangep()		const { return op3p()->castRange(); }	// op3 = Range of arrayed instants (NULL=not ranged)
     AstModule* modp()		const { return m_modp; }		// [AfterLink] = Pointer to module instantiated
-    void addPinsp(AstPin* pinp) { addOp1p(pinp); }
-    void addParamsp(AstPin* pinp) { addOp2p(pinp); }
-    void modp(AstModule* modp)	{ m_modp = modp; }
-    void modName(const string& name)	{ m_modName = name; }
-    void name(const string& name) 	{ m_name = name; }
+    void addPinsp(AstPin* nodep) { addOp1p(nodep); }
+    void addParamsp(AstPin* nodep) { addOp2p(nodep); }
+    void modp(AstModule* nodep)	{ m_modp = nodep; }
 };
 
 struct AstCellInline : public AstNode {

src/V3Inst.cpp

@@ -157,7 +157,11 @@ private:
 		nodep->addNextHere(newp);
 		// Remove ranging and fix name
 		newp->rangep()->unlinkFrBack()->deleteTree();
+		// Somewhat illogically, we need to rename the orignal name of the cell too.
+		// as that is the name users expect for dotting
+		// The spec says we add [x], but that won't work in C...
 		newp->name(newp->name()+"__"+cvtToStr(m_instNum));
+		newp->origName(newp->origName()+"__"+cvtToStr(m_instNum));
 		// Fixup pins
 		newp->pinsp()->iterateAndNext(*this);
 		if (debug()==9) { newp->dumpTree(cout,"newcell: "); cout<<endl; }

test_regress/t/t_inst_array.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -40,7 +40,14 @@ module t (/*AUTOARG*/
    end
 endmodule
 
+`ifdef USE_INLINE
+ `define INLINE_MODULE /*verilator inline_module*/
+`else
+ `define INLINE_MODULE /*verilator public_module*/
+`endif
+
 module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
+   `INLINE_MODULE
    wire bitout = (^ onebit) ^ (^ allbits);
 endmodule
 

test_regress/t/t_inst_array_inl0.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2006 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_inst_array.v");
+
+compile (
+	 v_flags2 => ['+define+NOUSE_INLINE',],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_inst_array_inl1.pl

@@ -1,13 +1,16 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003-2005 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 
+top_filename("t/t_inst_array.v");
+
 compile (
+	 v_flags2 => ['+define+USE_INLINE',],
 	 );
 
 execute (