From 6f48185a1fd672bfa89d27f1b99c337b0629904d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 1 Sep 2006 15:31:07 +0000 Subject: [PATCH] Fix arrayed instances git-svn-id: file://localhost/svn/verilator/trunk/verilator@774 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 4 +++- bin/verilator | 4 ++-- src/V3AstNodes.h | 11 +++++----- src/V3Inst.cpp | 4 ++++ test_regress/t/t_inst_array.v | 9 +++++++- test_regress/t/t_inst_array_inl0.pl | 21 +++++++++++++++++++ .../{t_inst_array.pl => t_inst_array_inl1.pl} | 5 ++++- 7 files changed, 48 insertions(+), 10 deletions(-) create mode 100644 test_regress/t/t_inst_array_inl0.pl rename test_regress/t/{t_inst_array.pl => t_inst_array_inl1.pl} (83%) diff --git a/Changes b/Changes index 0e40eb6bf..91b93657f 100644 --- a/Changes +++ b/Changes @@ -14,9 +14,11 @@ indicates the contributor was also the author of the fix; Thanks! *** Changed how internal functions are invoked to reduce aliasing. Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%. +**** Fix memory leak when destroying modules. [John Stroebel] + **** Fix coredump when unused modules have unused cells. [David Hewson] -**** Fix memory leak when destroying modules. [John Stroebel] +**** Fix 3.600 internal error with arrayed instances. [David Hewson] **** Fix $display %m name not matching Verilog name inside SystemC modules. diff --git a/bin/verilator b/bin/verilator index 75334375c..58dfe743a 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1115,8 +1115,8 @@ always @* to prevent these issues.) =head2 Dotted cross-hierarchy references Verilator supports dotted references to variables, functions and tasks in -different modules. However, references into named blocks and function-local -variables are not supported. +different modules. However, references into named blocks, function-local +variables, and arrayed instances are not supported. =head2 Latches diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 81d0dbba7..46c972083 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -650,17 +650,18 @@ public: virtual bool broken() const { return (m_modp && !m_modp->brokeExists()); } // ACCESSORS virtual string name() const { return m_name; } // * = Cell name + void name(const string& name) { m_name = name; } string origName() const { return m_origName; } // * = Original name + void origName(const string& name) { m_origName = name; } string modName() const { return m_modName; } // * = Instance name + void modName(const string& name) { m_modName = name; } AstPin* pinsp() const { return op1p()->castPin(); } // op1 = List of cell ports AstPin* paramsp() const { return op2p()->castPin(); } // op2 = List of parameter #(##) values AstRange* rangep() const { return op3p()->castRange(); } // op3 = Range of arrayed instants (NULL=not ranged) AstModule* modp() const { return m_modp; } // [AfterLink] = Pointer to module instantiated - void addPinsp(AstPin* pinp) { addOp1p(pinp); } - void addParamsp(AstPin* pinp) { addOp2p(pinp); } - void modp(AstModule* modp) { m_modp = modp; } - void modName(const string& name) { m_modName = name; } - void name(const string& name) { m_name = name; } + void addPinsp(AstPin* nodep) { addOp1p(nodep); } + void addParamsp(AstPin* nodep) { addOp2p(nodep); } + void modp(AstModule* nodep) { m_modp = nodep; } }; struct AstCellInline : public AstNode { diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 041e39bf7..3eca5babb 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -157,7 +157,11 @@ private: nodep->addNextHere(newp); // Remove ranging and fix name newp->rangep()->unlinkFrBack()->deleteTree(); + // Somewhat illogically, we need to rename the orignal name of the cell too. + // as that is the name users expect for dotting + // The spec says we add [x], but that won't work in C... newp->name(newp->name()+"__"+cvtToStr(m_instNum)); + newp->origName(newp->origName()+"__"+cvtToStr(m_instNum)); // Fixup pins newp->pinsp()->iterateAndNext(*this); if (debug()==9) { newp->dumpTree(cout,"newcell: "); cout< ['+define+NOUSE_INLINE',], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_inst_array.pl b/test_regress/t/t_inst_array_inl1.pl similarity index 83% rename from test_regress/t/t_inst_array.pl rename to test_regress/t/t_inst_array_inl1.pl index 115c3ed81..628e7a0e1 100755 --- a/test_regress/t/t_inst_array.pl +++ b/test_regress/t/t_inst_array_inl1.pl @@ -1,13 +1,16 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ +# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2005 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # General Public License or the Perl Artistic License. +top_filename("t/t_inst_array.v"); + compile ( + v_flags2 => ['+define+USE_INLINE',], ); execute (