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Merge branch 'master' into develop-v5

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This commit is contained in:
Wilson Snyder 2022-06-04 12:17:29 -04:00
commit 6769106881
2 changed files with 8 additions and 14 deletions
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6
test_regress/t/t_gen_forif.v
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@ -29,7 +29,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin always @ (posedge clk) begin
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x %x %x %x\n", $time, cyc, crc, Result, Result2); $write("[%0t] cyc==%0d crc=%x %x %x\n", $time, cyc, crc, Result, Result2);
`endif `endif
cyc <= cyc + 1; cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@ -62,10 +62,10 @@ module Test (clk, Value, Result);
reg Internal; reg Internal;
assign Result = Internal ^ clk; assign Result = Internal;
always @(posedge clk) always @(posedge clk)
Internal <= #1 Value; Internal <= Value;
endmodule endmodule
module Test_wrap1 (clk, Value, Result); module Test_wrap1 (clk, Value, Result);

16
test_regress/t/t_gen_intdot.v
View File

@ -40,14 +40,6 @@ module t (/*AUTOARG*/
end end
end end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
$dumpvars(12, t);
end
`endif
endmodule endmodule
module Generate (clk, value, result); module Generate (clk, value, result);
@ -57,10 +49,10 @@ module Generate (clk, value, result);
reg Internal; reg Internal;
assign result = Internal ^ clk; assign result = Internal;
always @(posedge clk) always @(posedge clk)
Internal <= #1 value; Internal <= value;
endmodule endmodule
module Checker (clk, value); module Checker (clk, value);
@ -89,7 +81,9 @@ module Genit (clk, value, result);
`ifndef ATSIM // else unsupported `ifndef ATSIM // else unsupported
`ifndef NC // else unsupported `ifndef NC // else unsupported
`define WITH_FOR_GENVAR `ifndef IVERILOG // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif `endif
`endif `endif