From 32100a3c913133adff55d3a5eccd15552c245ef5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 4 Jun 2022 12:16:42 -0400 Subject: [PATCH] Tests: Fix racy tests for develop-v5. --- test_regress/t/t_gen_forif.v | 6 +++--- test_regress/t/t_gen_intdot.v | 16 +++++----------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 5e70a0ee3..73fa55138 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -29,7 +29,7 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x %x %x %x\n", $time, cyc, crc, Result, Result2); + $write("[%0t] cyc==%0d crc=%x %x %x\n", $time, cyc, crc, Result, Result2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; @@ -62,10 +62,10 @@ module Test (clk, Value, Result); reg Internal; - assign Result = Internal ^ clk; + assign Result = Internal; always @(posedge clk) - Internal <= #1 Value; + Internal <= Value; endmodule module Test_wrap1 (clk, Value, Result); diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index 240672ccd..249af3417 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -40,14 +40,6 @@ module t (/*AUTOARG*/ end end -//`define WAVES -`ifdef WAVES - initial begin - $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); - $dumpvars(12, t); - end -`endif - endmodule module Generate (clk, value, result); @@ -57,10 +49,10 @@ module Generate (clk, value, result); reg Internal; - assign result = Internal ^ clk; + assign result = Internal; always @(posedge clk) - Internal <= #1 value; + Internal <= value; endmodule module Checker (clk, value); @@ -89,7 +81,9 @@ module Genit (clk, value, result); `ifndef ATSIM // else unsupported `ifndef NC // else unsupported - `define WITH_FOR_GENVAR + `ifndef IVERILOG // else unsupported + `define WITH_FOR_GENVAR + `endif `endif `endif