github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-03 21:27:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

tests: Avoid assuming a timescale.

Browse Source
This commit is contained in:
Wilson Snyder 2020-04-07 20:55:47 -04:00
parent 914a6edd33
commit 608d5a87d1
2 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
examples/make_tracing_sc/sc_main.cpp
View File

@ -90,7 +90,7 @@ int sc_main(int argc, char* argv[]) {
// You must do one evaluation before enabling waves, in order to allow // You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing. // SystemC to interconnect everything for testing.
#if (SYSTEMC_VERSION>=20070314) #if (SYSTEMC_VERSION>=20070314)
sc_start(1,SC_NS); sc_start(1, SC_NS);
#else #else
sc_start(1); sc_start(1);
#endif #endif
@ -118,15 +118,16 @@ int sc_main(int argc, char* argv[]) {
#endif #endif
// Apply inputs // Apply inputs
if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) { if (sc_time_stamp() > sc_time(1, SC_NS)
&& sc_time_stamp() < sc_time(10, SC_NS)) {
reset_l = !1; // Assert reset reset_l = !1; // Assert reset
} else if (VL_TIME_Q() > 1) { } else {
reset_l = !0; // Deassert reset reset_l = !0; // Deassert reset
} }
// Simulate 1ns // Simulate 1ns
#if (SYSTEMC_VERSION>=20070314) #if (SYSTEMC_VERSION>=20070314)
sc_start(1,SC_NS); sc_start(1, SC_NS);
#else #else
sc_start(1); sc_start(1);
#endif #endif

4
test_regress/driver.pl
View File

@ -1798,7 +1798,8 @@ sub _make_top_v {
$self->_read_inputs_v(); $self->_read_inputs_v();
my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},"; my $fh = IO::File->new(">$self->{top_shell_filename}")
or die "%Error: $! $self->{top_shell_filename},";
print $fh "module top;\n"; print $fh "module top;\n";
foreach my $inp (sort (keys %{$self->{inputs}})) { foreach my $inp (sort (keys %{$self->{inputs}})) {
print $fh " reg ${inp};\n"; print $fh " reg ${inp};\n";
@ -2007,6 +2008,7 @@ sub files_identical {
$l1[$l] =~ s/\r/<#013>/mig; $l1[$l] =~ s/\r/<#013>/mig;
$l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig; $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig;
$l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig; $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig;
$l1[$l] =~ s/CPU Time: +[0-9.]+ seconds[^\n]+/CPU Time: ###/mig;
if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) { if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) {
splice @l1, $l+1; # Trunc rest splice @l1, $l+1; # Trunc rest
last; last;