diff --git a/examples/make_tracing_sc/sc_main.cpp b/examples/make_tracing_sc/sc_main.cpp index 31145a17f..30f47f2bc 100644 --- a/examples/make_tracing_sc/sc_main.cpp +++ b/examples/make_tracing_sc/sc_main.cpp @@ -90,7 +90,7 @@ int sc_main(int argc, char* argv[]) { // You must do one evaluation before enabling waves, in order to allow // SystemC to interconnect everything for testing. #if (SYSTEMC_VERSION>=20070314) - sc_start(1,SC_NS); + sc_start(1, SC_NS); #else sc_start(1); #endif @@ -118,15 +118,16 @@ int sc_main(int argc, char* argv[]) { #endif // Apply inputs - if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) { + if (sc_time_stamp() > sc_time(1, SC_NS) + && sc_time_stamp() < sc_time(10, SC_NS)) { reset_l = !1; // Assert reset - } else if (VL_TIME_Q() > 1) { + } else { reset_l = !0; // Deassert reset } // Simulate 1ns #if (SYSTEMC_VERSION>=20070314) - sc_start(1,SC_NS); + sc_start(1, SC_NS); #else sc_start(1); #endif diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 7b1f82649..2884f55b0 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1798,7 +1798,8 @@ sub _make_top_v { $self->_read_inputs_v(); - my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},"; + my $fh = IO::File->new(">$self->{top_shell_filename}") + or die "%Error: $! $self->{top_shell_filename},"; print $fh "module top;\n"; foreach my $inp (sort (keys %{$self->{inputs}})) { print $fh " reg ${inp};\n"; @@ -2007,6 +2008,7 @@ sub files_identical { $l1[$l] =~ s/\r/<#013>/mig; $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig; $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig; + $l1[$l] =~ s/CPU Time: +[0-9.]+ seconds[^\n]+/CPU Time: ###/mig; if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) { splice @l1, $l+1; # Trunc rest last;