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Fix module parameter name collision (#3854) (#3855)

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James Shi 2023-01-20 18:38:59 -05:00 committed by GitHub
parent be53eec5ca
commit 5ef373500f
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4 changed files with 42 additions and 3 deletions
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2
src/V3EmitCHeaders.cpp
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@ -147,7 +147,7 @@ class EmitCHeader final : public EmitCConstInit {
if (!VN_IS(modp, Class)) { // Classes use CFuncs with isConstructor/isDestructor
const string& name = prefixNameProtect(modp);
putsDecoration("\n// CONSTRUCTORS\n");
puts(name + "(" + symClassName() + "* symsp, const char* name);\n");
puts(name + "(" + symClassName() + "* symsp, const char* v__name);\n");
puts("~" + name + "();\n");
puts("VL_UNCOPYABLE(" + name + ");\n");
}

4
src/V3EmitCImp.cpp
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@ -250,8 +250,8 @@ class EmitCImp final : EmitCFunc {
"(" + modName + "* vlSelf);");
puts("\n");
puts(modName + "::" + modName + "(" + symClassName() + "* symsp, const char* name)\n");
puts(" : VerilatedModule{name}\n");
puts(modName + "::" + modName + "(" + symClassName() + "* symsp, const char* v__name)\n");
puts(" : VerilatedModule{v__name}\n");
ofp()->indentInc();
for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {

21
test_regress/t/t_name_collision.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

18
test_regress/t/t_name_collision.v Normal file
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@ -0,0 +1,18 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module HasNameParam
#(parameter name /*verilator public*/ = 0)
();
endmodule
module t ();
HasNameParam a();
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule