Fix display optimization ignoring side effects (#4585).

Changes

@@ -43,6 +43,7 @@ Verilator 5.017 devel
 * Fix shift to remove operation side effects (#4563).
 * Fix compile warning on unused member function variable (#4567).
 * Fix method narrowing conversion compiler error (#4568).
+* Fix display optimization ignoring side effects (#4585).
 * Fix preprocessor to show `line 2 on resumed file.
 
 

src/V3Ast.h

@@ -2132,6 +2132,8 @@ public:
     virtual bool isPredictOptimizable() const { return !isTimingControl(); }
     // Else a $display, etc, that must be ordered with other displays
     virtual bool isPure() { return true; }
+    // Iff isPure on current node and any nextp()
+    bool isPureAndNext() { return isPure() && (!nextp() || nextp()->isPure()); }
     // Else a AstTime etc that can't be substituted out
     virtual bool isSubstOptimizable() const { return true; }
     // An event control, delay, wait, etc.

src/V3Const.cpp

@@ -3149,6 +3149,8 @@ private:
         // right line numbers, nor scopeNames as might be different scopes (late in process)
         if (!m_doCpp && pformatp->exprsp()) return false;
         if (!m_doCpp && nformatp->exprsp()) return false;
+        if (pformatp->exprsp() && !pformatp->exprsp()->isPureAndNext()) return false;
+        if (nformatp->exprsp() && !nformatp->exprsp()->isPureAndNext()) return false;
         // Avoid huge merges
         static constexpr int DISPLAY_MAX_MERGE_LENGTH = 500;
         if (pformatp->text().length() + nformatp->text().length() > DISPLAY_MAX_MERGE_LENGTH)

test_regress/t/t_display_impure.out

@@ -0,0 +1,3 @@
+          1
+          2
+*-* All Finished *-*

test_regress/t/t_display_impure.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_display_impure.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+function integer f;
+   static integer i = 0;
+   return ++i;
+endfunction
+
+module t;
+   initial begin
+      $display("%d", f());
+      $display("%d", f());
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule