Fix method narrowing conversion compiler error (#4568).

Changes

@@ -42,6 +42,7 @@ Verilator 5.017 devel
 * Fix instance arrays connecting to array of structs (#4557). [raphmaster]
 * Fix shift to remove operation side effects (#4563).
 * Fix compile warning on unused member function variable (#4567).
+* Fix method narrowing conversion compiler error (#4568).
 * Fix preprocessor to show `line 2 on resumed file.
 
 

src/V3Cast.cpp

@@ -162,6 +162,11 @@ private:
         ensureLower32Cast(nodep);
         nodep->user1(1);
     }
+    void visit(AstConsPackMember* nodep) override {
+        iterateChildren(nodep);
+        if (VN_IS(nodep->rhsp()->dtypep()->skipRefp(), BasicDType)) ensureCast(nodep->rhsp());
+        nodep->user1(1);
+    }
     void visit(AstExprStmt* nodep) override {
         iterateChildren(nodep);
         nodep->user1(1);

src/V3EmitCFunc.h

@@ -1130,6 +1130,10 @@ public:
         // Extending a value of the same word width is just a NOP.
         if (const AstClassRefDType* const classDtypep = VN_CAST(nodep->dtypep(), ClassRefDType)) {
             puts("(" + classDtypep->cType("", false, false) + ")(");
+        } else if (nodep->size() <= VL_BYTESIZE) {
+            puts("(CData)(");
+        } else if (nodep->size() <= VL_SHORTSIZE) {
+            puts("(SData)(");
         } else if (nodep->size() <= VL_IDATASIZE) {
             puts("(IData)(");
         } else {

test_regress/t/t_struct_cons_cast.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_struct_cons_cast.v

@@ -0,0 +1,57 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class uvm_policy;
+   typedef enum {
+                 NEVER,
+                 STARTED,
+                 FINISHED
+                 } recursion_state_e;
+endclass
+
+typedef enum {
+              UVM_DEFAULT_POLICY = 0,
+              UVM_DEEP           = (1<<16),
+              UVM_SHALLOW        = (1<<17),
+              UVM_REFERENCE      = (1<<18)
+              } uvm_recursion_policy_enum;
+
+class Cls;
+   typedef struct {
+      uvm_policy::recursion_state_e state;
+      bit         ret_val;
+   } state_info_t;
+
+   state_info_t m_recur_states/*[uvm_object][uvm_object]*/[uvm_recursion_policy_enum];
+
+   automatic function uvm_recursion_policy_enum get_recursion_policy();
+      return UVM_DEEP;
+   endfunction
+
+   automatic function bit get_ret_val();
+      return $c(1);
+   endfunction
+
+   automatic function void test();
+      bit ret_val;
+      ret_val = $c1(1);
+      // See issue #4568
+      m_recur_states[get_recursion_policy()] = '{uvm_policy::FINISHED, ret_val};
+   endfunction
+
+endclass
+
+module t;
+
+   initial begin
+      Cls c;
+      c = new;
+      $display("%p", c);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule