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Ignore "// verilator" comments alone on endif lines.

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Wilson Snyder 2008-06-11 13:09:36 -04:00
parent 52912c6329
commit 5a1a5a7d97
3 changed files with 5 additions and 1 deletions
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2
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@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett] **** Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett]
**** Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair]
* Verilator 3.664 2008/05/08 * Verilator 3.664 2008/05/08
**** Fix missing file in kit. **** Fix missing file in kit.

1
src/verilog.l
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@ -529,6 +529,7 @@ escid \\[^ \t\f\r\n]+
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */
<V95,V01,V05,S05,PSL>{ <V95,V01,V05,S05,PSL>{
"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
"/*verilator clock_enable*/" {yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;} "/*verilator clock_enable*/" {yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;}
"/*verilator coverage_block_off*/" {yylval.fileline = CRELINE(); return yVL_COVER_OFF;} "/*verilator coverage_block_off*/" {yylval.fileline = CRELINE(); return yVL_COVER_OFF;}
"/*verilator full_case*/" {yylval.fileline = CRELINE(); return yVL_FULL_CASE;} "/*verilator full_case*/" {yylval.fileline = CRELINE(); return yVL_FULL_CASE;}

3
test_regress/t/t_extend.v
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@ -71,7 +71,8 @@ module t (/*AUTOARG*/
printf("In systemc_dtor\n"); printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n"); printf("*-* All Finished *-*\n");
`verilog `verilog
`endif
// Test verilator comment after a endif
`endif // verilator
endmodule endmodule