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Tests: Add t_interface_hidden

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This commit is contained in:
Wilson Snyder 2024-12-02 18:31:46 -05:00
parent a64660a530
commit 59fd238a05
4 changed files with 158 additions and 55 deletions
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18
test_regress/t/t_interface_hidden.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

76
test_regress/t/t_interface_hidden.v Normal file
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@ -0,0 +1,76 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc ifc(); // Cell name hides interface's name
assign ifc.ifi = 55;
sub sub (.isub(ifc)); // Cell name hides module's name
int om;
mod_or_type mot (.*);
hides_with_type hides_type();
hides_with_decl hides_decl();
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 20) begin
if (om != 22) $stop;
if (mot.LOCAL != 22) $stop;
if (ifc.ifo != 55) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
(
ifc isub
);
always @* begin
isub.ifo = isub.ifi;
end
endmodule
module mod_or_type(output int om);
localparam LOCAL = 22;
initial om = 22;
endmodule
module hides_with_type();
typedef int ifc; // Hides interface
typedef int mod_or_type; // Hides module
ifc /*=int*/ hides_ifc;
mod_or_type /*=int*/ hides_mod;
initial hides_ifc = 33;
initial hides_mod = 44;
endmodule
module hides_with_decl();
int ifc; // Hides interface
int mod_or_type; // Hides module
initial ifc = 66;
initial mod_or_type = 77;
endmodule
interface ifc;
localparam LOCAL = 12;
int ifi;
int ifo;
endinterface

110
test_regress/t/t_unpacked_concat.v
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@ -6,90 +6,90 @@
module t (/*AUTOARG*/); module t (/*AUTOARG*/);
typedef int AI3[1:3]; typedef int ai3_t[1:3];
AI3 A3; ai3_t a3;
int A9[1:9]; int a9[1:9];
logic [2:0] s0; logic [2:0] s0;
logic [2:0] s1[1:3]; logic [2:0] s1[1:3];
logic [2:0] s2[3:1]; logic [2:0] s1b[3:1];
logic [2:0] s3[2:8]; logic [2:0] s3[2:8];
logic [2:0] s4[8:2]; logic [2:0] s3b[8:2];
initial begin initial begin
s0 = 3'd1; s0 = 3'd1;
s1[1] = 3'd2; s1[1] = 3'd2;
s1[2] = 3'd3; s1[2] = 3'd3;
s1[3] = 3'd4; s1[3] = 3'd4;
s2[1] = 3'd5; s1b[1] = 3'd5;
s2[2] = 3'd6; s1b[2] = 3'd6;
s2[3] = 3'd7; s1b[3] = 3'd7;
A3 = '{1, 2, 3}; a3 = '{1, 2, 3};
A9 = {A3, 4, 5, A3, 6}; a9 = {a3, 4, 5, a3, 6};
if (A9[1] != 1) $stop; if (a9[1] != 1) $stop;
if (A9[2] != 2) $stop; if (a9[2] != 2) $stop;
if (A9[3] != 3) $stop; if (a9[3] != 3) $stop;
if (A9[4] != 4) $stop; if (a9[4] != 4) $stop;
if (A9[5] != 5) $stop; if (a9[5] != 5) $stop;
if (A9[6] != 1) $stop; if (a9[6] != 1) $stop;
if (A9[7] != 2) $stop; if (a9[7] != 2) $stop;
if (A9[8] != 3) $stop; if (a9[8] != 3) $stop;
if (A9[9] != 6) $stop; if (a9[9] != 6) $stop;
s3 = {s0, s1, s2}; s3 = {s0, s1, s1b};
if (s3[2] != s0) $stop; if (s3[2] != s0) $stop;
if (s3[3] != s1[1]) $stop; if (s3[3] != s1[1]) $stop;
if (s3[4] != s1[2]) $stop; if (s3[4] != s1[2]) $stop;
if (s3[5] != s1[3]) $stop; if (s3[5] != s1[3]) $stop;
if (s3[6] != s2[3]) $stop; if (s3[6] != s1b[3]) $stop;
if (s3[7] != s2[2]) $stop; if (s3[7] != s1b[2]) $stop;
if (s3[8] != s2[1]) $stop; if (s3[8] != s1b[1]) $stop;
s3[2:8] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]}; s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
if (s3[2] != s0) $stop; if (s3[2] != s0) $stop;
if (s3[3] != s1[1]) $stop; if (s3[3] != s1[1]) $stop;
if (s3[4] != s1[2]) $stop; if (s3[4] != s1[2]) $stop;
if (s3[5] != s1[3]) $stop; if (s3[5] != s1[3]) $stop;
if (s3[6] != s2[3]) $stop; if (s3[6] != s1b[3]) $stop;
if (s3[7] != s2[2]) $stop; if (s3[7] != s1b[2]) $stop;
if (s3[8] != s2[1]) $stop; if (s3[8] != s1b[1]) $stop;
s3 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]}; s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
if (s3[2] != s0) $stop; if (s3[2] != s0) $stop;
if (s3[3] != s1[1]) $stop; if (s3[3] != s1[1]) $stop;
if (s3[4] != s1[2]) $stop; if (s3[4] != s1[2]) $stop;
if (s3[5] != s1[3]) $stop; if (s3[5] != s1[3]) $stop;
if (s3[6] != s2[3]) $stop; if (s3[6] != s1b[3]) $stop;
if (s3[7] != s2[2]) $stop; if (s3[7] != s1b[2]) $stop;
if (s3[8] != s2[1]) $stop; if (s3[8] != s1b[1]) $stop;
s4 = {s0, s1, s2}; s3b = {s0, s1, s1b};
if (s4[8] != s0) $stop; if (s3b[8] != s0) $stop;
if (s4[7] != s1[1]) $stop; if (s3b[7] != s1[1]) $stop;
if (s4[6] != s1[2]) $stop; if (s3b[6] != s1[2]) $stop;
if (s4[5] != s1[3]) $stop; if (s3b[5] != s1[3]) $stop;
if (s4[4] != s2[3]) $stop; if (s3b[4] != s1b[3]) $stop;
if (s4[3] != s2[2]) $stop; if (s3b[3] != s1b[2]) $stop;
if (s4[2] != s2[1]) $stop; if (s3b[2] != s1b[1]) $stop;
s4[8:2] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]}; s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
if (s4[8] != s0) $stop; if (s3b[8] != s0) $stop;
if (s4[7] != s1[1]) $stop; if (s3b[7] != s1[1]) $stop;
if (s4[6] != s1[2]) $stop; if (s3b[6] != s1[2]) $stop;
if (s4[5] != s1[3]) $stop; if (s3b[5] != s1[3]) $stop;
if (s4[4] != s2[3]) $stop; if (s3b[4] != s1b[3]) $stop;
if (s4[3] != s2[2]) $stop; if (s3b[3] != s1b[2]) $stop;
if (s4[2] != s2[1]) $stop; if (s3b[2] != s1b[1]) $stop;
s4 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]}; s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
if (s4[8] != s0) $stop; if (s3b[8] != s0) $stop;
if (s4[7] != s1[1]) $stop; if (s3b[7] != s1[1]) $stop;
if (s4[6] != s1[2]) $stop; if (s3b[6] != s1[2]) $stop;
if (s4[5] != s1[3]) $stop; if (s3b[5] != s1[3]) $stop;
if (s4[4] != s2[3]) $stop; if (s3b[4] != s1b[3]) $stop;
if (s4[3] != s2[2]) $stop; if (s3b[3] != s1b[2]) $stop;
if (s4[2] != s2[1]) $stop; if (s3b[2] != s1b[1]) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

9
test_regress/t/t_unpacked_init.v
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@ -14,6 +14,8 @@ module t (/*AUTOARG*/);
int a3[1] = '{16}; int a3[1] = '{16};
int a4[1] = {17}; int a4[1] = {17};
int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}};
initial begin initial begin
`checkh(a1[0], 12); `checkh(a1[0], 12);
`checkh(a1[1], 13); `checkh(a1[1], 13);
@ -25,6 +27,13 @@ module t (/*AUTOARG*/);
`checkh(a4[0], 17); `checkh(a4[0], 17);
`checkh(a5[0][0], 10);
`checkh(a5[0][1], 11);
`checkh(a5[0][2], 12);
`checkh(a5[1][0], 13);
`checkh(a5[1][1], 14);
`checkh(a5[1][2], 15);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end