From 59fd238a05eaf7ed0b9c828f912b1272191bd077 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 Dec 2024 18:31:46 -0500 Subject: [PATCH] Tests: Add t_interface_hidden --- test_regress/t/t_interface_hidden.py | 18 +++++ test_regress/t/t_interface_hidden.v | 76 ++++++++++++++++++ test_regress/t/t_unpacked_concat.v | 110 +++++++++++++-------------- test_regress/t/t_unpacked_init.v | 9 +++ 4 files changed, 158 insertions(+), 55 deletions(-) create mode 100755 test_regress/t/t_interface_hidden.py create mode 100644 test_regress/t/t_interface_hidden.v diff --git a/test_regress/t/t_interface_hidden.py b/test_regress/t/t_interface_hidden.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_interface_hidden.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_hidden.v b/test_regress/t/t_interface_hidden.v new file mode 100644 index 000000000..04b460d92 --- /dev/null +++ b/test_regress/t/t_interface_hidden.v @@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc ifc(); // Cell name hides interface's name + assign ifc.ifi = 55; + + sub sub (.isub(ifc)); // Cell name hides module's name + + int om; + + mod_or_type mot (.*); + + hides_with_type hides_type(); + hides_with_decl hides_decl(); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + if (om != 22) $stop; + if (mot.LOCAL != 22) $stop; + if (ifc.ifo != 55) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + ( + ifc isub + ); + always @* begin + isub.ifo = isub.ifi; + end +endmodule + +module mod_or_type(output int om); + localparam LOCAL = 22; + initial om = 22; +endmodule + +module hides_with_type(); + typedef int ifc; // Hides interface + typedef int mod_or_type; // Hides module + + ifc /*=int*/ hides_ifc; + mod_or_type /*=int*/ hides_mod; + + initial hides_ifc = 33; + initial hides_mod = 44; +endmodule + +module hides_with_decl(); + int ifc; // Hides interface + int mod_or_type; // Hides module + + initial ifc = 66; + initial mod_or_type = 77; +endmodule + +interface ifc; + localparam LOCAL = 12; + int ifi; + int ifo; +endinterface diff --git a/test_regress/t/t_unpacked_concat.v b/test_regress/t/t_unpacked_concat.v index 468518ab2..f1ca793b5 100644 --- a/test_regress/t/t_unpacked_concat.v +++ b/test_regress/t/t_unpacked_concat.v @@ -6,90 +6,90 @@ module t (/*AUTOARG*/); - typedef int AI3[1:3]; - AI3 A3; - int A9[1:9]; + typedef int ai3_t[1:3]; + ai3_t a3; + int a9[1:9]; logic [2:0] s0; logic [2:0] s1[1:3]; - logic [2:0] s2[3:1]; + logic [2:0] s1b[3:1]; logic [2:0] s3[2:8]; - logic [2:0] s4[8:2]; + logic [2:0] s3b[8:2]; initial begin s0 = 3'd1; s1[1] = 3'd2; s1[2] = 3'd3; s1[3] = 3'd4; - s2[1] = 3'd5; - s2[2] = 3'd6; - s2[3] = 3'd7; + s1b[1] = 3'd5; + s1b[2] = 3'd6; + s1b[3] = 3'd7; - A3 = '{1, 2, 3}; - A9 = {A3, 4, 5, A3, 6}; - if (A9[1] != 1) $stop; - if (A9[2] != 2) $stop; - if (A9[3] != 3) $stop; - if (A9[4] != 4) $stop; - if (A9[5] != 5) $stop; - if (A9[6] != 1) $stop; - if (A9[7] != 2) $stop; - if (A9[8] != 3) $stop; - if (A9[9] != 6) $stop; + a3 = '{1, 2, 3}; + a9 = {a3, 4, 5, a3, 6}; + if (a9[1] != 1) $stop; + if (a9[2] != 2) $stop; + if (a9[3] != 3) $stop; + if (a9[4] != 4) $stop; + if (a9[5] != 5) $stop; + if (a9[6] != 1) $stop; + if (a9[7] != 2) $stop; + if (a9[8] != 3) $stop; + if (a9[9] != 6) $stop; - s3 = {s0, s1, s2}; + s3 = {s0, s1, s1b}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; - if (s3[6] != s2[3]) $stop; - if (s3[7] != s2[2]) $stop; - if (s3[8] != s2[1]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s3[2:8] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]}; + s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; - if (s3[6] != s2[3]) $stop; - if (s3[7] != s2[2]) $stop; - if (s3[8] != s2[1]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s3 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]}; + s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; - if (s3[6] != s2[3]) $stop; - if (s3[7] != s2[2]) $stop; - if (s3[8] != s2[1]) $stop; + if (s3[6] != s1b[3]) $stop; + if (s3[7] != s1b[2]) $stop; + if (s3[8] != s1b[1]) $stop; - s4 = {s0, s1, s2}; - if (s4[8] != s0) $stop; - if (s4[7] != s1[1]) $stop; - if (s4[6] != s1[2]) $stop; - if (s4[5] != s1[3]) $stop; - if (s4[4] != s2[3]) $stop; - if (s4[3] != s2[2]) $stop; - if (s4[2] != s2[1]) $stop; + s3b = {s0, s1, s1b}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; - s4[8:2] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]}; - if (s4[8] != s0) $stop; - if (s4[7] != s1[1]) $stop; - if (s4[6] != s1[2]) $stop; - if (s4[5] != s1[3]) $stop; - if (s4[4] != s2[3]) $stop; - if (s4[3] != s2[2]) $stop; - if (s4[2] != s2[1]) $stop; + s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; - s4 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]}; - if (s4[8] != s0) $stop; - if (s4[7] != s1[1]) $stop; - if (s4[6] != s1[2]) $stop; - if (s4[5] != s1[3]) $stop; - if (s4[4] != s2[3]) $stop; - if (s4[3] != s2[2]) $stop; - if (s4[2] != s2[1]) $stop; + s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; + if (s3b[8] != s0) $stop; + if (s3b[7] != s1[1]) $stop; + if (s3b[6] != s1[2]) $stop; + if (s3b[5] != s1[3]) $stop; + if (s3b[4] != s1b[3]) $stop; + if (s3b[3] != s1b[2]) $stop; + if (s3b[2] != s1b[1]) $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_unpacked_init.v b/test_regress/t/t_unpacked_init.v index ae7243ad1..e9d052a51 100644 --- a/test_regress/t/t_unpacked_init.v +++ b/test_regress/t/t_unpacked_init.v @@ -14,6 +14,8 @@ module t (/*AUTOARG*/); int a3[1] = '{16}; int a4[1] = {17}; + int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}}; + initial begin `checkh(a1[0], 12); `checkh(a1[1], 13); @@ -25,6 +27,13 @@ module t (/*AUTOARG*/); `checkh(a4[0], 17); + `checkh(a5[0][0], 10); + `checkh(a5[0][1], 11); + `checkh(a5[0][2], 12); + `checkh(a5[1][0], 13); + `checkh(a5[1][1], 14); + `checkh(a5[1][2], 15); + $write("*-* All Finished *-*\n"); $finish; end