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Tests: Add t_interface_hidden
This commit is contained in:
Wilson Snyder
parent
a64660a530
commit
59fd238a05
18
test_regress/t/t_interface_hidden.py
Executable file
18
test_regress/t/t_interface_hidden.py
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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76
test_regress/t/t_interface_hidden.v
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76
test_regress/t/t_interface_hidden.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc ifc(); // Cell name hides interface's name
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assign ifc.ifi = 55;
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sub sub (.isub(ifc)); // Cell name hides module's name
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int om;
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mod_or_type mot (.*);
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hides_with_type hides_type();
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hides_with_decl hides_decl();
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 20) begin
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if (om != 22) $stop;
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if (mot.LOCAL != 22) $stop;
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if (ifc.ifo != 55) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub
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(
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ifc isub
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);
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always @* begin
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isub.ifo = isub.ifi;
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end
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endmodule
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module mod_or_type(output int om);
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localparam LOCAL = 22;
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initial om = 22;
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endmodule
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module hides_with_type();
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typedef int ifc; // Hides interface
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typedef int mod_or_type; // Hides module
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ifc /*=int*/ hides_ifc;
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mod_or_type /*=int*/ hides_mod;
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initial hides_ifc = 33;
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initial hides_mod = 44;
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endmodule
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module hides_with_decl();
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int ifc; // Hides interface
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int mod_or_type; // Hides module
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initial ifc = 66;
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initial mod_or_type = 77;
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endmodule
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interface ifc;
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localparam LOCAL = 12;
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int ifi;
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int ifo;
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endinterface
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@ -6,90 +6,90 @@
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module t (/*AUTOARG*/);
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typedef int AI3[1:3];
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AI3 A3;
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int A9[1:9];
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typedef int ai3_t[1:3];
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ai3_t a3;
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int a9[1:9];
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logic [2:0] s0;
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logic [2:0] s1[1:3];
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logic [2:0] s2[3:1];
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logic [2:0] s1b[3:1];
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logic [2:0] s3[2:8];
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logic [2:0] s4[8:2];
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logic [2:0] s3b[8:2];
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initial begin
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s0 = 3'd1;
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s1[1] = 3'd2;
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s1[2] = 3'd3;
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s1[3] = 3'd4;
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s2[1] = 3'd5;
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s2[2] = 3'd6;
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s2[3] = 3'd7;
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s1b[1] = 3'd5;
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s1b[2] = 3'd6;
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s1b[3] = 3'd7;
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A3 = '{1, 2, 3};
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A9 = {A3, 4, 5, A3, 6};
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if (A9[1] != 1) $stop;
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if (A9[2] != 2) $stop;
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if (A9[3] != 3) $stop;
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if (A9[4] != 4) $stop;
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if (A9[5] != 5) $stop;
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if (A9[6] != 1) $stop;
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if (A9[7] != 2) $stop;
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if (A9[8] != 3) $stop;
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if (A9[9] != 6) $stop;
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a3 = '{1, 2, 3};
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a9 = {a3, 4, 5, a3, 6};
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if (a9[1] != 1) $stop;
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if (a9[2] != 2) $stop;
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if (a9[3] != 3) $stop;
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if (a9[4] != 4) $stop;
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if (a9[5] != 5) $stop;
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if (a9[6] != 1) $stop;
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if (a9[7] != 2) $stop;
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if (a9[8] != 3) $stop;
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if (a9[9] != 6) $stop;
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s3 = {s0, s1, s2};
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s3 = {s0, s1, s1b};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s2[3]) $stop;
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if (s3[7] != s2[2]) $stop;
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if (s3[8] != s2[1]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s3[2:8] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]};
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s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s2[3]) $stop;
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if (s3[7] != s2[2]) $stop;
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if (s3[8] != s2[1]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s3 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]};
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s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s2[3]) $stop;
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if (s3[7] != s2[2]) $stop;
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if (s3[8] != s2[1]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s4 = {s0, s1, s2};
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if (s4[8] != s0) $stop;
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if (s4[7] != s1[1]) $stop;
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if (s4[6] != s1[2]) $stop;
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if (s4[5] != s1[3]) $stop;
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if (s4[4] != s2[3]) $stop;
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if (s4[3] != s2[2]) $stop;
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if (s4[2] != s2[1]) $stop;
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s3b = {s0, s1, s1b};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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s4[8:2] = {s0, s1[1:2], s1[3], s2[3], s2[2:1]};
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if (s4[8] != s0) $stop;
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if (s4[7] != s1[1]) $stop;
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if (s4[6] != s1[2]) $stop;
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if (s4[5] != s1[3]) $stop;
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if (s4[4] != s2[3]) $stop;
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if (s4[3] != s2[2]) $stop;
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if (s4[2] != s2[1]) $stop;
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s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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s4 = {s0, s1[1], s1[2:3], s2[3:2], s2[1]};
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if (s4[8] != s0) $stop;
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if (s4[7] != s1[1]) $stop;
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if (s4[6] != s1[2]) $stop;
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if (s4[5] != s1[3]) $stop;
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if (s4[4] != s2[3]) $stop;
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if (s4[3] != s2[2]) $stop;
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if (s4[2] != s2[1]) $stop;
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s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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@ -14,6 +14,8 @@ module t (/*AUTOARG*/);
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int a3[1] = '{16};
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int a4[1] = {17};
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int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}};
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initial begin
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`checkh(a1[0], 12);
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`checkh(a1[1], 13);
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@ -25,6 +27,13 @@ module t (/*AUTOARG*/);
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`checkh(a4[0], 17);
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`checkh(a5[0][0], 10);
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`checkh(a5[0][1], 11);
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`checkh(a5[0][2], 12);
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`checkh(a5[1][0], 13);
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`checkh(a5[1][1], 14);
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`checkh(a5[1][2], 15);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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