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Wilson Snyder 2024-09-19 17:58:37 -04:00
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docs/guide/example_sc.rst
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@ -28,6 +28,7 @@ Now, let's create an example Verilog, and SystemC wrapper file:
cat >sc_main.cpp <<'EOF' cat >sc_main.cpp <<'EOF'
#include "Vour.h" #include "Vour.h"
using namespace sc_core;
int sc_main(int argc, char** argv) { int sc_main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};