From 49bccb5f1b5a42ade4f9d88b861cde21c4e32fa2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 19 Sep 2024 17:58:37 -0400
Subject: [PATCH] Commentary

---
 docs/guide/example_sc.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst
index 441c8e542..f844f4a25 100644
--- a/docs/guide/example_sc.rst
+++ b/docs/guide/example_sc.rst
@@ -28,6 +28,7 @@ Now, let's create an example Verilog, and SystemC wrapper file:
 
      cat >sc_main.cpp <<'EOF'
        #include "Vour.h"
+       using namespace sc_core;
        int sc_main(int argc, char** argv) {
            Verilated::commandArgs(argc, argv);
            sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};