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Update error as misnamed port dtype might be interface

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This commit is contained in:
Wilson Snyder 2024-12-02 07:35:44 -05:00
parent b16b48f458
commit 4781a6046a
3 changed files with 3 additions and 3 deletions
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2
src/V3LinkDot.cpp
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@ -4137,7 +4137,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
if (foundp) {
nodep->v3error("Expecting a data type: " << nodep->prettyNameQ());
} else {
nodep->v3error("Can't find typedef: " << nodep->prettyNameQ());
nodep->v3error("Can't find typedef/interface: " << nodep->prettyNameQ());
}
}
}

2
src/verilog.y
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@ -1520,7 +1520,7 @@ port<nodep>: // ==IEEE: port
// // IEEE: interface_port_header port_identifier { unpacked_dimension }
// // Expanded interface_port_header
// // We use instantCb here because the non-port form looks just like a module instantiation
portDirNetE id/*interface*/ portSig variable_dimensionListE sigAttrListE
portDirNetE id/*interface*/ portSig variable_dimensionListE sigAttrListE
{ // VAR for now, but V3LinkCells may call setIfcaeRef on it later
$$ = $3; VARDECL(VAR); VARIO(NONE);
AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, "", *$2};

2
test_regress/t/t_typedef_no_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef: 'sometype'
%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef/interface: 'sometype'
10 | sometype p;
| ^~~~~~~~
%Error: Exiting due to