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Wilson Snyder 2023-05-04 19:04:38 -04:00
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13
README.rst
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@ -59,17 +59,16 @@ files, the "Verilated" code.
These Verilated C++/SystemC files are then compiled by a C++ compiler These Verilated C++/SystemC files are then compiled by a C++ compiler
(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper
file to instantiate the Verilated model. Executing the resulting executable file, to instantiate the Verilated model. Executing the resulting
performs the design simulation. Verilator also supports linking Verilated executable performs the design simulation. Verilator also supports linking
generated libraries, optionally encrypted, into other simulators. Verilated generated libraries, optionally encrypted, into other simulators.
Verilator may not be the best choice if you are expecting a full-featured Verilator may not be the best choice if you are expecting a full-featured
replacement for a closed-source Verilog simulator, needs SDF annotation, replacement for a closed-source Verilog simulator, needs SDF annotation,
mixed-signal simulation, or are doing a quick class project (we recommend mixed-signal simulation, or are doing a quick class project (we recommend
`Icarus Verilog`_ for classwork.) However, if you are looking for a path `Icarus Verilog`_ for classwork.) However, if you are looking for a path
to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
synthesizable designs containing limited verification constructs, Verilator designs, Verilator is the tool for you.
is the tool for you.
Performance Performance
@ -85,11 +84,11 @@ as `Icarus Verilog`_. Another 2-10x speedup might be gained from
multithreading (yielding 200-1000x total over interpreted simulators). multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus the Verilator has typically similar or better performance versus the
closed-source Verilog simulators (Carbon Design Systems Carbonator, closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator,
Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
computes rather than licenses. Thus, Verilator gives you the best computes rather than licenses. Thus, Verilator gives you the best
cycles/dollar. simulation cycles/dollar.
Installation & Documentation Installation & Documentation

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docs/guide/faq.rst
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@ -356,8 +356,8 @@ Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"?
You need to link your compiled Verilated code against the You need to link your compiled Verilated code against the
:code:`verilated.cpp` file found in the include directory of the Verilator :code:`verilated.cpp` file found in the include directory of the Verilator
kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which
should be part of your Makefile's link rule. If you use :vlopt:`--exe`, should be part of your Makefile's link rule. If you use :vlopt:`--exe` or
this is done for you. :vlopt:`--binary`, this is done for you.
Is the PLI supported? Is the PLI supported?

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docs/spelling.txt
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@ -602,6 +602,7 @@ genvar
genvars genvars
getenv getenv
getline getline
ggdb
gmake gmake
gmon gmon
gotFinish gotFinish