From 3bb4e34044d7fde17bea675cdbc1e6e26a1f0723 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 4 May 2023 19:04:38 -0400 Subject: [PATCH] Commentary --- README.rst | 13 ++++++------- docs/guide/faq.rst | 4 ++-- docs/spelling.txt | 1 + 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/README.rst b/README.rst index e45c73fb9..1b8cc8435 100644 --- a/README.rst +++ b/README.rst @@ -59,17 +59,16 @@ files, the "Verilated" code. These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper -file to instantiate the Verilated model. Executing the resulting executable -performs the design simulation. Verilator also supports linking Verilated -generated libraries, optionally encrypted, into other simulators. +file, to instantiate the Verilated model. Executing the resulting +executable performs the design simulation. Verilator also supports linking +Verilated generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, needs SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend `Icarus Verilog`_ for classwork.) However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of -synthesizable designs containing limited verification constructs, Verilator -is the tool for you. +designs, Verilator is the tool for you. Performance @@ -85,11 +84,11 @@ as `Icarus Verilog`_. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or better performance versus the -closed-source Verilog simulators (Carbon Design Systems Carbonator, +closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus, Verilator gives you the best -cycles/dollar. +simulation cycles/dollar. Installation & Documentation diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 4b161bc2d..621b0e3b5 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -356,8 +356,8 @@ Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"? You need to link your compiled Verilated code against the :code:`verilated.cpp` file found in the include directory of the Verilator kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which -should be part of your Makefile's link rule. If you use :vlopt:`--exe`, -this is done for you. +should be part of your Makefile's link rule. If you use :vlopt:`--exe` or +:vlopt:`--binary`, this is done for you. Is the PLI supported? diff --git a/docs/spelling.txt b/docs/spelling.txt index f4660bed4..85817af63 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -602,6 +602,7 @@ genvar genvars getenv getline +ggdb gmake gmon gotFinish