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This commit is contained in:
Wilson Snyder 2021-11-13 10:46:25 -05:00
parent 27883b52d6
commit 3a5cbd5b67
198 changed files with 638 additions and 638 deletions
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12
test_regress/t/t_xml_debugcheck.out
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@ -842,13 +842,13 @@
<varref fl="d64" loc="d,64,3,64,4" name="t.e" dtype_id="5"/>
</assignpost>
</cfunc>
<cfunc fl="d22" loc="d,22,17,22,18" name="_initial__TOP__2">
<cfunc fl="d22" loc="d,22,19,22,20" name="_initial__TOP__2">
<var fl="d27" loc="d,27,11,27,14" name="t.all" dtype_id="4" vartype="string" origName="t__DOT__all"/>
<var fl="d51" loc="d,51,17,51,18" name="t.unnamedblk1.e" dtype_id="2" vartype="my_t" origName="t__DOT__unnamedblk1__DOT__e"/>
<var fl="d48" loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="4" vartype="string" origName="__Vtemp_h########__0"/>
<assign fl="d22" loc="d,22,17,22,18" dtype_id="3">
<const fl="d22" loc="d,22,17,22,18" name="32&apos;sh0" dtype_id="7"/>
<varref fl="d22" loc="d,22,17,22,18" name="t.cyc" dtype_id="3"/>
<assign fl="d22" loc="d,22,19,22,20" dtype_id="3">
<const fl="d22" loc="d,22,19,22,20" name="32&apos;sh0" dtype_id="7"/>
<varref fl="d22" loc="d,22,19,22,20" name="t.cyc" dtype_id="3"/>
</assign>
<assign fl="d31" loc="d,31,9,31,10" dtype_id="5">
<const fl="d31" loc="d,31,11,31,14" name="4&apos;h3" dtype_id="5"/>
@ -1411,7 +1411,7 @@
<varref fl="d14" loc="d,14,10,14,13" name="clk" dtype_id="8"/>
<varref fl="d14" loc="d,14,10,14,13" name="__Vclklast__TOP__clk" dtype_id="8"/>
</assign>
<ccall fl="d22" loc="d,22,17,22,18" func="_initial__TOP__2"/>
<ccall fl="d22" loc="d,22,19,22,20" func="_initial__TOP__2"/>
</cfunc>
<cfunc fl="d10" loc="d,10,8,10,9" name="_eval_settle"/>
<cfunc fl="d10" loc="d,10,8,10,9" name="_final"/>
@ -1544,7 +1544,7 @@
</range>
</unpackarraydtype>
<refdtype fl="d51" loc="d,51,12,51,16" id="16" name="my_t" sub_dtype_id="2"/>
<basicdtype fl="d22" loc="d,22,17,22,18" id="7" name="logic" left="31" right="0" signed="true"/>
<basicdtype fl="d22" loc="d,22,19,22,20" id="7" name="logic" left="31" right="0" signed="true"/>
<basicdtype fl="d64" loc="d,64,3,64,4" id="5" name="logic" left="31" right="0"/>
<basicdtype fl="d62" loc="d,62,14,62,16" id="8" name="logic" left="31" right="0"/>
<basicdtype fl="d67" loc="d,67,13,67,17" id="10" name="logic" left="31" right="0"/>