diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v
index 032785ac5..3cc26f133 100644
--- a/test_regress/t/t_EXAMPLE.v
+++ b/test_regress/t/t_EXAMPLE.v
@@ -22,7 +22,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -47,11 +47,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -63,7 +63,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
diff --git a/test_regress/t/t_alw_split_rst.v b/test_regress/t/t_alw_split_rst.v
index b0f411f53..5e39edbcb 100644
--- a/test_regress/t/t_alw_split_rst.v
+++ b/test_regress/t/t_alw_split_rst.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -44,11 +44,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -60,7 +60,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a
diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v
index 2c4cd8350..c6105c7b4 100644
--- a/test_regress/t/t_array_mda.v
+++ b/test_regress/t/t_array_mda.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -26,11 +26,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -57,7 +57,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd
diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v
index b46935b34..79dbb15e0 100644
--- a/test_regress/t/t_array_rev.v
+++ b/test_regress/t/t_array_rev.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc=0;
+ integer cyc = 0;
// verilator lint_off LITENDIAN
logic arrd [0:1] = '{ 1'b1, 1'b0 };
// verilator lint_on LITENDIAN
diff --git a/test_regress/t/t_assign_slice_overflow.v b/test_regress/t/t_assign_slice_overflow.v
index 8cee5b0d3..816aa6b98 100644
--- a/test_regress/t/t_assign_slice_overflow.v
+++ b/test_regress/t/t_assign_slice_overflow.v
@@ -29,7 +29,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;
diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v
index 6c474516a..278003ca4 100644
--- a/test_regress/t/t_assoc.v
+++ b/test_regress/t/t_assoc.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
integer i;
diff --git a/test_regress/t/t_assoc2.v b/test_regress/t/t_assoc2.v
index 4c938a35a..8cea07e6b 100644
--- a/test_regress/t/t_assoc2.v
+++ b/test_regress/t/t_assoc2.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
// associative array of an associative array
logic [31:0] a [logic [31:0]][logic [63:0]];
diff --git a/test_regress/t/t_assoc_wildcard_unsup.v b/test_regress/t/t_assoc_wildcard_unsup.v
index d29a50bf8..d17eaf3c1 100644
--- a/test_regress/t/t_assoc_wildcard_unsup.v
+++ b/test_regress/t/t_assoc_wildcard_unsup.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
integer i;
diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v
index f943829c2..d8f9d9ad8 100644
--- a/test_regress/t/t_bitsel_slice.v
+++ b/test_regress/t/t_bitsel_slice.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc21e42d85441511
diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v
index 12335f6ac..1041a0281 100644
--- a/test_regress/t/t_case_deep.v
+++ b/test_regress/t/t_case_deep.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -42,11 +42,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -57,7 +57,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v
index 8f38669e8..74d91c740 100644
--- a/test_regress/t/t_case_dupitems.v
+++ b/test_regress/t/t_case_dupitems.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v
index 59879dd2e..49a70997b 100644
--- a/test_regress/t/t_case_inside.v
+++ b/test_regress/t/t_case_inside.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -21,10 +21,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2);
+ $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
@@ -32,7 +32,7 @@ module t (/*AUTOARG*/
sum <= 64'h0;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v
index 8ba5b85d8..024d1ebca 100644
--- a/test_regress/t/t_case_nest.v
+++ b/test_regress/t/t_case_nest.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -20,10 +20,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
+ $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup
diff --git a/test_regress/t/t_case_onehot.v b/test_regress/t/t_case_onehot.v
index 2f71d68e9..35288267a 100644
--- a/test_regress/t/t_case_onehot.v
+++ b/test_regress/t/t_case_onehot.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v
index 44e0a11bc..ab8f6eabe 100644
--- a/test_regress/t/t_case_reducer.v
+++ b/test_regress/t/t_case_reducer.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v
index c6daa0688..171236ad5 100644
--- a/test_regress/t/t_case_wild.v
+++ b/test_regress/t/t_case_wild.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -20,9 +20,9 @@ module t (/*AUTOARG*/
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
+ //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v
index 7c3c8edf7..2b469f7cd 100644
--- a/test_regress/t/t_case_write1.v
+++ b/test_regress/t/t_case_write1.v
@@ -21,7 +21,7 @@ module t (/*AUTOARG*/
t_case_write1_tasks tasks ();
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
@@ -30,9 +30,9 @@ module t (/*AUTOARG*/
end
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+ //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});
diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v
index 98d50c2b5..7027ee9d9 100644
--- a/test_regress/t/t_case_write2.v
+++ b/test_regress/t/t_case_write2.v
@@ -21,7 +21,7 @@ module t (/*AUTOARG*/
t_case_write2_tasks tasks ();
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
@@ -30,9 +30,9 @@ module t (/*AUTOARG*/
end
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+ //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"});
diff --git a/test_regress/t/t_castdyn_enum.v b/test_regress/t/t_castdyn_enum.v
index 47e61cf98..2a68c93bf 100644
--- a/test_regress/t/t_castdyn_enum.v
+++ b/test_regress/t/t_castdyn_enum.v
@@ -36,7 +36,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
i = $cast(en, cyc);
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d i=%0d en=%0d\n",$time, cyc, i, en);
+ $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en);
`endif
cyc <= cyc + 1;
if (cyc == 10) begin
diff --git a/test_regress/t/t_chg_first.v b/test_regress/t/t_chg_first.v
index 77015defd..41cde7a1a 100644
--- a/test_regress/t/t_chg_first.v
+++ b/test_regress/t/t_chg_first.v
@@ -38,7 +38,7 @@ module t (/*AUTOARG*/
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
if (_mode==1) begin
- //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
+ //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//if (ord2 == 2 && ord7 != 7) $stop;
end
end
diff --git a/test_regress/t/t_clk_2in.v b/test_regress/t/t_clk_2in.v
index 25bd369ae..21bc8b253 100644
--- a/test_regress/t/t_clk_2in.v
+++ b/test_regress/t/t_clk_2in.v
@@ -85,7 +85,7 @@ module `t2 (
integer vn = 0;
integer vpn = 0;
task clear;
-`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
+`ifdef TEST_VERBOSE $display("[%0t] clear\n", $time); `endif
p0 = 0;
p1 = 0;
p01 = 0;
@@ -98,7 +98,7 @@ module `t2 (
endtask
`define display_counts(text) begin \
- $write("[%0t] ",$time); \
+ $write("[%0t] ", $time); \
`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
$write(text); \
$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \
diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v
index 0c7877790..9cedf8e33 100644
--- a/test_regress/t/t_clk_dpulse.v
+++ b/test_regress/t/t_clk_dpulse.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
// verilator lint_off GENCLK
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg genclk;
// verilator lint_off MULTIDRIVEN
reg [7:0] set_both;
diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v
index 9572c35e6..f991e87eb 100644
--- a/test_regress/t/t_clk_dsp.v
+++ b/test_regress/t/t_clk_dsp.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
// verilator lint_off GENCLK
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg [7:0] padd;
reg dsp_ph1, dsp_ph2, dsp_reset;
diff --git a/test_regress/t/t_clk_first.v b/test_regress/t/t_clk_first.v
index 84b6f050b..92285011c 100644
--- a/test_regress/t/t_clk_first.v
+++ b/test_regress/t/t_clk_first.v
@@ -72,7 +72,7 @@ module t_clk (/*AUTOARG*/
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
- $write("[%0t] t_clk: Running\n",$time);
+ $write("[%0t] t_clk: Running\n", $time);
`endif
reset_int_ <= 1;
end
diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v
index b676228ae..4c2d253de 100644
--- a/test_regress/t/t_clk_gater.v
+++ b/test_regress/t/t_clk_gater.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
@@ -55,7 +55,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v
index caf25288c..487920783 100644
--- a/test_regress/t/t_clk_latch.v
+++ b/test_regress/t/t_clk_latch.v
@@ -80,7 +80,7 @@ module t (/*AUTOARG*/
end
end
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
diff --git a/test_regress/t/t_clk_latchgate.v b/test_regress/t/t_clk_latchgate.v
index 120db757f..b18af26c5 100644
--- a/test_regress/t/t_clk_latchgate.v
+++ b/test_regress/t/t_clk_latchgate.v
@@ -28,7 +28,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
@@ -69,18 +69,18 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
+ $write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+ $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v
index 55173b573..bb496db57 100644
--- a/test_regress/t/t_clk_powerdn.v
+++ b/test_regress/t/t_clk_powerdn.v
@@ -58,10 +58,10 @@ module t (/*AUTOARG*/
end
end
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated);
+ $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n", $time,reset_l,cyc,clkgate_e1f,count,countgated);
`endif
cyc <= cyc + 8'd1;
case (cyc)
diff --git a/test_regress/t/t_clk_vecgen1.v b/test_regress/t/t_clk_vecgen1.v
index fd4cd4bad..8c7535c07 100644
--- a/test_regress/t/t_clk_vecgen1.v
+++ b/test_regress/t/t_clk_vecgen1.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -33,11 +33,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -48,7 +48,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_concat_sel.v b/test_regress/t/t_concat_sel.v
index 33dc12a99..605794d85 100644
--- a/test_regress/t/t_concat_sel.v
+++ b/test_regress/t/t_concat_sel.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -45,11 +45,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -61,7 +61,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
diff --git a/test_regress/t/t_const_op_red_scope.v b/test_regress/t/t_const_op_red_scope.v
index e36cd4d8a..7ac8d9699 100644
--- a/test_regress/t/t_const_op_red_scope.v
+++ b/test_regress/t/t_const_op_red_scope.v
@@ -22,7 +22,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -81,11 +81,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -97,7 +97,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h118c5809c7856d78
diff --git a/test_regress/t/t_const_opt.v b/test_regress/t/t_const_opt.v
index 2b953aa8d..eb6097355 100644
--- a/test_regress/t/t_const_opt.v
+++ b/test_regress/t/t_const_opt.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,12 +37,12 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("o %b", o);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t(/*AUTOARG*/
else if (cyc < 99) begin
end
else begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha916d9291821c6e0
diff --git a/test_regress/t/t_const_opt_cov.v b/test_regress/t/t_const_opt_cov.v
index c939ad806..0d3790fed 100644
--- a/test_regress/t/t_const_opt_cov.v
+++ b/test_regress/t/t_const_opt_cov.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha2601675a6ae4972
diff --git a/test_regress/t/t_const_opt_or.v b/test_regress/t/t_const_opt_or.v
index 0f9077960..7ed622dc7 100644
--- a/test_regress/t/t_const_opt_or.v
+++ b/test_regress/t/t_const_opt_or.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -45,11 +45,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -59,7 +59,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc97b141ac5d6d7d
diff --git a/test_regress/t/t_const_opt_red.v b/test_regress/t/t_const_opt_red.v
index b8d2725ac..6405e0c92 100644
--- a/test_regress/t/t_const_opt_red.v
+++ b/test_regress/t/t_const_opt_red.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -129,14 +129,14 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11);
$display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11);
$display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -174,12 +174,12 @@ module t(/*AUTOARG*/
if (z6 != '1) $stop;
if (z7 != '0) $stop;
if (match1_o != match2_o) begin
- $write("[%0t] cyc==%0d m1=%d != m2=%d\n",$time, cyc, match1_o, match2_o);
+ $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o);
$stop;
end
end
else begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h727fb78d09c1981e
diff --git a/test_regress/t/t_const_opt_shortcut.v b/test_regress/t/t_const_opt_shortcut.v
index 5690188f7..5ad27558e 100644
--- a/test_regress/t/t_const_opt_shortcut.v
+++ b/test_regress/t/t_const_opt_shortcut.v
@@ -16,7 +16,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t(/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (import_func1() != 1) $stop; // this must be the first call
if (import_func3() != 1) $stop; // this must be the first call
diff --git a/test_regress/t/t_display_merge.v b/test_regress/t/t_display_merge.v
index 9d5b1e3ec..0704e7728 100644
--- a/test_regress/t/t_display_merge.v
+++ b/test_regress/t/t_display_merge.v
@@ -23,14 +23,14 @@ module t (/*AUTOARG*/);
$write(" 1=%0d a=%m 1=%0d", one, one);
$display(" 1=%0d b=%m 1=%0d", one, one);
$display(" pre");
- $display(" t=%0d",$time);
- $display(" t2=%0d",$time);
+ $display(" t=%0d", $time);
+ $display(" t2=%0d", $time);
$display(" post");
- $display(" t3=%0d",$time);
- $display(" t4=%0d t5=%0d",$time,$time,$time);
+ $display(" t3=%0d", $time);
+ $display(" t4=%0d t5=%0d", $time,$time,$time);
$display("m");
- $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
- $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+ $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
+ $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$display("mm");
$display("");
@@ -38,14 +38,14 @@ module t (/*AUTOARG*/);
$write(" a=%m");
$write(" b=%m");
$write(" pre");
- $write(" t=%0d",$time);
- $write(" t2=%0d",$time);
+ $write(" t=%0d", $time);
+ $write(" t2=%0d", $time);
$write(" post");
- $write(" t3=%0d",$time);
- $write(" t4=%0d t5=%0d",$time,$time,$time);
+ $write(" t3=%0d", $time);
+ $write(" t4=%0d t5=%0d", $time,$time,$time);
$write("m");
- $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
- $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time);
+ $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
+ $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time);
$display("mm");
$display("very very very very very very very very very very very very very very very very very very very very very very");
diff --git a/test_regress/t/t_display_realtime.v b/test_regress/t/t_display_realtime.v
index 9dbcff308..ec16d2e91 100644
--- a/test_regress/t/t_display_realtime.v
+++ b/test_regress/t/t_display_realtime.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
diff --git a/test_regress/t/t_display_wide.v b/test_regress/t/t_display_wide.v
index 026ebecf2..c356ab0e4 100644
--- a/test_regress/t/t_display_wide.v
+++ b/test_regress/t/t_display_wide.v
@@ -10,21 +10,21 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
- crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
+ crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
- $write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
- //Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+ $write("[%0t] cyc==%0d crc=%x%x%x%x\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
+ $write("[%0t] cyc==%0d crc=%b%b%b%b\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
+ //Unsupported: $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_dpi_var.v b/test_regress/t/t_dpi_var.v
index a5fc89111..7909867bc 100644
--- a/test_regress/t/t_dpi_var.v
+++ b/test_regress/t/t_dpi_var.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
wire monclk = ~clk;
@@ -25,7 +25,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
+ $write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n", $time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
@@ -91,8 +91,8 @@ module sub (/*AUTOARG*/
$c("mon_class_name(this->name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
- $c("mon_register_a(\"in\",&",in,",false);");
- $c("mon_register_a(\"fr_a\",&",fr_a,",true);");
+ $c("mon_register_a(\"in\", &", in, ", false);");
+ $c("mon_register_a(\"fr_a\", &", fr_a, ", true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v
index a24a83453..68fe7fb25 100644
--- a/test_regress/t/t_dynarray.v
+++ b/test_regress/t/t_dynarray.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
integer i;
string v;
diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v
index c65452f7d..0ba86f13c 100644
--- a/test_regress/t/t_embed1.v
+++ b/test_regress/t/t_embed1.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -82,11 +82,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result,
+ $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -100,7 +100,7 @@ module t (/*AUTOARG*/
end
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;
diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v
index ae9774734..20fa8a9ed 100644
--- a/test_regress/t/t_emit_constw.v
+++ b/test_regress/t/t_emit_constw.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -67,11 +67,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -147,7 +147,7 @@ module t (/*AUTOARG*/
w17 = w17 >>> 1;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v
index a8b75326b..bd9eb5da5 100644
--- a/test_regress/t/t_enum_large_methods.v
+++ b/test_regress/t/t_enum_large_methods.v
@@ -18,7 +18,7 @@ module t (/*AUTOARG*/
ELARGE = 'hf00d
} my_t;
- integer cyc=0;
+ integer cyc = 0;
my_t e;
string all;
diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v
index 37697ddf7..5d30a0534 100644
--- a/test_regress/t/t_enum_type_methods.v
+++ b/test_regress/t/t_enum_type_methods.v
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
E04 = 4
} my_t;
- integer cyc=0;
+ integer cyc = 0;
my_t e;
int arrayfits [e.num]; // Check can use as constant
diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v
index 1ed24e25d..f4a8e362c 100644
--- a/test_regress/t/t_extend.v
+++ b/test_regress/t/t_extend.v
@@ -13,14 +13,14 @@ module t (/*AUTOARG*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
- cyc <= cyc+8'd1;
+ cyc <= cyc + 8'd1;
// coverage testing
if (one) begin end
@@ -33,7 +33,7 @@ module t (/*AUTOARG*/
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
- $c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
+ $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");");
c_worked <= $c("this->my_function()");
c_wider <= $c9("0x10");
`else
diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v
index fb6d400c1..a12826fc6 100644
--- a/test_regress/t/t_extend_class.v
+++ b/test_regress/t/t_extend_class.v
@@ -10,14 +10,14 @@ module t (/*AUTOARG*/
);
input clk;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg [31:0] in;
wire [31:0] out;
t_extend_class_v sub (.in(in), .out(out));
always @ (posedge clk) begin
- cyc <= cyc+8'd1;
+ cyc <= cyc + 8'd1;
if (cyc == 8'd1) begin
in <= 32'h10;
end
@@ -43,7 +43,7 @@ module t_extend_class_v (/*AUTOARG*/
always @* begin
// When "in" changes, call my method
- out = $c("this->m_myobjp->my_math(",in,")");
+ out = $c("this->m_myobjp->my_math(", in, ")");
end
`systemc_header
diff --git a/test_regress/t/t_flag_compiler.v b/test_regress/t/t_flag_compiler.v
index 27d49b279..df8446ba5 100644
--- a/test_regress/t/t_flag_compiler.v
+++ b/test_regress/t/t_flag_compiler.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [89:0] in;
@@ -33,7 +33,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
+ $write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
diff --git a/test_regress/t/t_flag_csplit.v b/test_regress/t/t_flag_csplit.v
index b1ad77045..e25102a36 100644
--- a/test_regress/t/t_flag_csplit.v
+++ b/test_regress/t/t_flag_csplit.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
parameter CNT = 5;
@@ -36,7 +36,7 @@ module t (/*AUTOARG*/
else if (cyc==99) begin
`define EXPECTED_SUM 32'h1239
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, w[CNT]);
+ $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, w[CNT]);
`endif
if (w[CNT] !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v
index 0e2084e9d..fabb7b3b9 100644
--- a/test_regress/t/t_for_break.v
+++ b/test_regress/t/t_for_break.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -32,11 +32,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
if (out0!==out3) $stop;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h293e9f9798e97da0
diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v
index b2eba60c3..b217dd246 100644
--- a/test_regress/t/t_for_funcbound.v
+++ b/test_regress/t/t_for_funcbound.v
@@ -22,7 +22,7 @@ module t (/*AUTOARG*/
reg [7:0] char;
integer loc;
begin
- $write("[%0t] ",$time);
+ $write("[%0t] ", $time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
diff --git a/test_regress/t/t_for_local.v b/test_regress/t/t_for_local.v
index 94a2eb99d..f7deaa4eb 100644
--- a/test_regress/t/t_for_local.v
+++ b/test_regress/t/t_for_local.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
@@ -18,7 +18,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
- $write("[%0t] t_loop: Running\n",$time);
+ $write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;
diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v
index 24cd98a0c..23912a81f 100644
--- a/test_regress/t/t_for_loop.v
+++ b/test_regress/t/t_for_loop.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
- $write("[%0t] t_loop: Running\n",$time);
+ $write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;
diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v
index 05b1ac9f8..4fb6c33c9 100644
--- a/test_regress/t/t_func_check.v
+++ b/test_regress/t/t_func_check.v
@@ -10,7 +10,7 @@ module t (
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
@@ -20,7 +20,7 @@ module t (
always @ (posedge clk) begin
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v
index 30d4ecc04..85cccec96 100644
--- a/test_regress/t/t_func_endian.v
+++ b/test_regress/t/t_func_endian.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -55,7 +55,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;
diff --git a/test_regress/t/t_func_first.v b/test_regress/t/t_func_first.v
index 6aedc2fcf..f882fac13 100644
--- a/test_regress/t/t_func_first.v
+++ b/test_regress/t/t_func_first.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
reg set_in_task;
always @ (posedge clk) begin
diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v
index d5464771c..6a9a00dc9 100644
--- a/test_regress/t/t_func_graphcirc.v
+++ b/test_regress/t/t_func_graphcirc.v
@@ -7,7 +7,7 @@
module t (clk);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v
index cae0da0a5..1f08b9af1 100644
--- a/test_regress/t/t_func_noinl.v
+++ b/test_regress/t/t_func_noinl.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_func_outfirst.v b/test_regress/t/t_func_outfirst.v
index 589435311..68f6ee7a8 100644
--- a/test_regress/t/t_func_outfirst.v
+++ b/test_regress/t/t_func_outfirst.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -43,11 +43,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -59,7 +59,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3a74e9d34771ad93
diff --git a/test_regress/t/t_func_plog.v b/test_regress/t/t_func_plog.v
index 59b210b4b..db13bd781 100644
--- a/test_regress/t/t_func_plog.v
+++ b/test_regress/t/t_func_plog.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg rst_n;
@@ -41,11 +41,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
rst_n <= ~1'b0;
if (cyc==0) begin
// Setup
@@ -60,7 +60,7 @@ module t (/*AUTOARG*/
if (pos1 !== pos2) $stop;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v
index a60f1fbd7..5da1f012a 100644
--- a/test_regress/t/t_func_rand.v
+++ b/test_regress/t/t_func_rand.v
@@ -20,7 +20,7 @@ module t (clk, Rand);
input [7:0] idx;
begin
`ifdef verilator
- QxRand32 = $c("this->QxRandTbl(",tbl,",",idx,")");
+ QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")");
`else
QxRand32 = 32'hfeed0fad;
`endif
diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v
index 5c6c54e69..6732caf7b 100644
--- a/test_regress/t/t_func_return.v
+++ b/test_regress/t/t_func_return.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -31,11 +31,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -47,7 +47,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
diff --git a/test_regress/t/t_func_sum.v b/test_regress/t/t_func_sum.v
index ccbab0594..cf5c8b644 100644
--- a/test_regress/t/t_func_sum.v
+++ b/test_regress/t/t_func_sum.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_gate_array.v b/test_regress/t/t_gate_array.v
index 0ea797e6b..f9673c861 100644
--- a/test_regress/t/t_gate_array.v
+++ b/test_regress/t/t_gate_array.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v
index 6b68b548a..3e485ce34 100644
--- a/test_regress/t/t_gate_implicit.v
+++ b/test_regress/t/t_gate_implicit.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
diff --git a/test_regress/t/t_gate_ormux.v b/test_regress/t/t_gate_ormux.v
index 7033c45fa..26d254632 100755
--- a/test_regress/t/t_gate_ormux.v
+++ b/test_regress/t/t_gate_ormux.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (rdata2 != rdata) $stop;
if (cyc==0) begin
// Setup
@@ -52,13 +52,13 @@ module t (/*AUTOARG*/
sum <= '0;
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h8977713eb467bc86
if (sum !== `EXPECTED_SUM) $stop;
end
else if (cyc == `SIM_CYCLES) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
$write("*-* All Finished *-*\n");
$finish;
end
diff --git a/test_regress/t/t_gen_alw.v b/test_regress/t/t_gen_alw.v
index b30c20a03..8bd091b7f 100644
--- a/test_regress/t/t_gen_alw.v
+++ b/test_regress/t/t_gen_alw.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -29,11 +29,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -44,7 +44,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v
index 8bf840544..4528eebab 100644
--- a/test_regress/t/t_gen_assign.v
+++ b/test_regress/t/t_gen_assign.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [31:0] sum;
@@ -27,10 +27,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v
index 4ca2596d7..5ea4631ff 100644
--- a/test_regress/t/t_gen_for.v
+++ b/test_regress/t/t_gen_for.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [7:0] crc;
genvar g;
@@ -28,7 +28,7 @@ module t (/*AUTOARG*/
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
+ //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
diff --git a/test_regress/t/t_gen_for0.v b/test_regress/t/t_gen_for0.v
index 08427d063..b822d60ee 100644
--- a/test_regress/t/t_gen_for0.v
+++ b/test_regress/t/t_gen_for0.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
Testit testit (/*AUTOINST*/
// Inputs
diff --git a/test_regress/t/t_gen_for1.v b/test_regress/t/t_gen_for1.v
index a7dc72e62..628213f38 100644
--- a/test_regress/t/t_gen_for1.v
+++ b/test_regress/t/t_gen_for1.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
wire b;
reg reset;
- integer cyc=0;
+ integer cyc = 0;
Testit testit (/*AUTOINST*/
// Outputs
diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v
index b71f4ffac..ad93479ff 100644
--- a/test_regress/t/t_gen_for_shuffle.v
+++ b/test_regress/t/t_gen_for_shuffle.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -33,11 +33,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -49,7 +49,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v
index 91e3a913f..3ffaa7085 100644
--- a/test_regress/t/t_gen_forif.v
+++ b/test_regress/t/t_gen_forif.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -29,12 +29,12 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
+ $write("[%0t] cyc==%0d crc=%x %x %x %x\n", $time, cyc, crc, Result, Result2);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {56'h0, Result, Result2}
- ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -46,7 +46,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
- $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h4af37965592f64f9) $stop;
$finish;
diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v
index e2fbbce2d..dbe517bc6 100644
--- a/test_regress/t/t_gen_inc.v
+++ b/test_regress/t/t_gen_inc.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
genvar g;
integer i;
diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v
index a4ffab809..16c509e8d 100644
--- a/test_regress/t/t_gen_intdot.v
+++ b/test_regress/t/t_gen_intdot.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
wire out;
reg in;
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
+ //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v
index a2f3886ca..917b6223c 100644
--- a/test_regress/t/t_gen_intdot2.v
+++ b/test_regress/t/t_gen_intdot2.v
@@ -11,14 +11,14 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
+ //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v
index f9adfd461..3e42ecf26 100644
--- a/test_regress/t/t_gen_local.v
+++ b/test_regress/t/t_gen_local.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
localparam N = 31;
diff --git a/test_regress/t/t_gen_lsb.v b/test_regress/t/t_gen_lsb.v
index b442483e6..d5d24fa90 100644
--- a/test_regress/t/t_gen_lsb.v
+++ b/test_regress/t/t_gen_lsb.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3db7bc8bfe61f983
diff --git a/test_regress/t/t_gen_upscope.v b/test_regress/t/t_gen_upscope.v
index b9479e540..f765423d8 100644
--- a/test_regress/t/t_gen_upscope.v
+++ b/test_regress/t/t_gen_upscope.v
@@ -36,7 +36,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
tag tag ();
b b ();
diff --git a/test_regress/t/t_if_deep.v b/test_regress/t/t_if_deep.v
index e8217c4a9..db7a37c0c 100644
--- a/test_regress/t/t_if_deep.v
+++ b/test_regress/t/t_if_deep.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v
index 963257cc4..e41a2f746 100644
--- a/test_regress/t/t_iff.v
+++ b/test_regress/t/t_iff.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -23,11 +23,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -39,7 +39,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he58508de5310b541
diff --git a/test_regress/t/t_inside_unpacked.v b/test_regress/t/t_inside_unpacked.v
index f15184aa5..0b0760fd8 100644
--- a/test_regress/t/t_inside_unpacked.v
+++ b/test_regress/t/t_inside_unpacked.v
@@ -22,7 +22,7 @@ module t(/*AUTOARG*/
if (MISS_INSIDE != 0) $stop;
end
- integer cyc=0;
+ integer cyc = 0;
int array [10];
logic l;
diff --git a/test_regress/t/t_inside_wild.v b/test_regress/t/t_inside_wild.v
index 7b377ffc6..f8b3e5f37 100644
--- a/test_regress/t/t_inside_wild.v
+++ b/test_regress/t/t_inside_wild.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3
diff --git a/test_regress/t/t_inst_aport.v b/test_regress/t/t_inst_aport.v
index 4773acb8b..1268ea960 100644
--- a/test_regress/t/t_inst_aport.v
+++ b/test_regress/t/t_inst_aport.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v
index a216bbe87..52cdfb4be 100644
--- a/test_regress/t/t_inst_array_partial.v
+++ b/test_regress/t/t_inst_array_partial.v
@@ -43,7 +43,7 @@ module t (/*AUTOARG*/
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -55,11 +55,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -71,7 +71,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v
index 3416a5915..31ae056ba 100644
--- a/test_regress/t/t_inst_ccall.v
+++ b/test_regress/t/t_inst_ccall.v
@@ -46,8 +46,8 @@ endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
- assign longout = $c32("(",narrow,"+1)");
- assign quadout = $c64("(",quad,"+1)");
+ assign longout = $c32("(", narrow, "+1)");
+ assign quadout = $c64("(", quad, "+1)");
`else
assign longout = narrow + 8'd1;
assign quadout = quad + 64'd1;
diff --git a/test_regress/t/t_inst_dff.v b/test_regress/t/t_inst_dff.v
index 0e7214233..00df717ed 100644
--- a/test_regress/t/t_inst_dff.v
+++ b/test_regress/t/t_inst_dff.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -42,11 +42,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -64,7 +64,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hbcfcebdb75ec9d32
diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v
index a96141c51..1663dc88f 100644
--- a/test_regress/t/t_inst_mnpipe.v
+++ b/test_regress/t/t_inst_mnpipe.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [2:0] sum;
@@ -20,7 +20,7 @@ module t (/*AUTOARG*/
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
+ //$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
diff --git a/test_regress/t/t_inst_notunsized.v b/test_regress/t/t_inst_notunsized.v
index 07d68a38f..d2fa6ff41 100644
--- a/test_regress/t/t_inst_notunsized.v
+++ b/test_regress/t/t_inst_notunsized.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v
index 7529608ae..39bdafa0d 100644
--- a/test_regress/t/t_inst_signed.v
+++ b/test_regress/t/t_inst_signed.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;
diff --git a/test_regress/t/t_inst_signed1.v b/test_regress/t/t_inst_signed1.v
index a1b1e4d5d..34cdaf2fc 100644
--- a/test_regress/t/t_inst_signed1.v
+++ b/test_regress/t/t_inst_signed1.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
wire signed o1;
wire signed o2;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
sub1 sub1 (.i(i), .o(o1));
sub2 sub2 (.i(o1), .o(o2));
diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v
index 1a56b6260..f05524451 100644
--- a/test_regress/t/t_inst_slice.v
+++ b/test_regress/t/t_inst_slice.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -31,11 +31,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum);
+ $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -47,7 +47,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb42b2f48a0a9375a
diff --git a/test_regress/t/t_interface_bind_public.v b/test_regress/t/t_interface_bind_public.v
index a95c01dfe..f20d70187 100644
--- a/test_regress/t/t_interface_bind_public.v
+++ b/test_regress/t/t_interface_bind_public.v
@@ -44,7 +44,7 @@ module t
.io_success(success)
);
- integer cyc=0;
+ integer cyc = 0;
always @ (posedge clk) begin
cyc = cyc + 1;
diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v
index d434618f5..70de3f0c3 100644
--- a/test_regress/t/t_interface_dups.v
+++ b/test_regress/t/t_interface_dups.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -57,11 +57,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -73,7 +73,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h6fd1bead9df31b07
diff --git a/test_regress/t/t_interface_gen2.v b/test_regress/t/t_interface_gen2.v
index 83d5643db..703a31a83 100644
--- a/test_regress/t/t_interface_gen2.v
+++ b/test_regress/t/t_interface_gen2.v
@@ -24,7 +24,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
+ $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
diff --git a/test_regress/t/t_interface_gen3.v b/test_regress/t/t_interface_gen3.v
index 59833d42c..7e8c92141 100644
--- a/test_regress/t/t_interface_gen3.v
+++ b/test_regress/t/t_interface_gen3.v
@@ -24,7 +24,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
+ $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v
index 4de2cd2c2..a3fabda04 100644
--- a/test_regress/t/t_interface_ref_trace.v
+++ b/test_regress/t/t_interface_ref_trace.v
@@ -23,7 +23,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
ifc intf_1(.*);
ifc intf_2(.*);
diff --git a/test_regress/t/t_math_clog2.v b/test_regress/t/t_math_clog2.v
index 713cb15f5..fdf68602e 100644
--- a/test_regress/t/t_math_clog2.v
+++ b/test_regress/t/t_math_clog2.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -37,11 +37,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
crc <= 64'h0;
if (`CLOG2(32'h0) != 0) $stop;
@@ -82,7 +82,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hcbc77bb9b3784ea0) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v
index bf5dc80e4..203c39416 100644
--- a/test_regress/t/t_math_cmp.v
+++ b/test_regress/t/t_math_cmp.v
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
.index_a (index_a),
.index_b (index_b));
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
@@ -117,7 +117,7 @@ module prover (
reg [7:0] exp;
reg [7:0] got;
- integer cyc=0;
+ integer cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v
index fd18e18aa..3ba29abb7 100644
--- a/test_regress/t/t_math_concat0.v
+++ b/test_regress/t/t_math_concat0.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
diff --git a/test_regress/t/t_math_cond_clean.v b/test_regress/t/t_math_cond_clean.v
index ca804c671..3c05b9dbf 100644
--- a/test_regress/t/t_math_cond_clean.v
+++ b/test_regress/t/t_math_cond_clean.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7cd85c944415d2ef
diff --git a/test_regress/t/t_math_cond_huge.v b/test_regress/t/t_math_cond_huge.v
index 22b9e65dd..f0e72273a 100644
--- a/test_regress/t/t_math_cond_huge.v
+++ b/test_regress/t/t_math_cond_huge.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -298,11 +298,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -313,7 +313,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v
index 11bd286eb..8580a714c 100644
--- a/test_regress/t/t_math_const.v
+++ b/test_regress/t/t_math_const.v
@@ -41,7 +41,7 @@ module t (/*AUTOARG*/
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
- $write("[%0t] t_const: Running\n",$time);
+ $write("[%0t] t_const: Running\n", $time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
diff --git a/test_regress/t/t_math_countbits.v b/test_regress/t/t_math_countbits.v
index 547263faa..33890f07a 100644
--- a/test_regress/t/t_math_countbits.v
+++ b/test_regress/t/t_math_countbits.v
@@ -70,7 +70,7 @@ module t(/*AUTOARG*/
logic [31:0] val = 32'h70008421;
- integer cyc=0;
+ integer cyc = 0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v
index 13f0f866f..1ab0e9495 100644
--- a/test_regress/t/t_math_eq.v
+++ b/test_regress/t/t_math_eq.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v
index 6ef2eb10a..e5019a4b0 100644
--- a/test_regress/t/t_math_imm.v
+++ b/test_regress/t/t_math_imm.v
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [63:0] sum;
@@ -48,7 +48,7 @@ module t (/*AUTOARG*/
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
+ $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
@@ -66,7 +66,7 @@ module t (/*AUTOARG*/
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v
index f83c751e0..a63ceb249 100644
--- a/test_regress/t/t_math_mul.v
+++ b/test_regress/t/t_math_mul.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -21,10 +21,10 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
+ $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n", $time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
diff --git a/test_regress/t/t_math_pick.v b/test_regress/t/t_math_pick.v
index 03ccdb90d..9f8aa5c17 100644
--- a/test_regress/t/t_math_pick.v
+++ b/test_regress/t/t_math_pick.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3ff4bf0e6407b281
diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v
index f181f6d21..9ecc6fd91 100644
--- a/test_regress/t/t_math_pow2.v
+++ b/test_regress/t/t_math_pow2.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -23,11 +23,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -39,7 +39,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h056ea1c5a63aff6a
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v
index 092bcbc0f..a7488e610 100644
--- a/test_regress/t/t_math_pow4.v
+++ b/test_regress/t/t_math_pow4.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
wire [31:0] y;
reg a;
@@ -23,7 +23,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d a=%x y=%x\n",$time, cyc, a, y);
+ $write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v
index bae1119c9..46a6b8d3a 100644
--- a/test_regress/t/t_math_precedence.v
+++ b/test_regress/t/t_math_precedence.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -105,7 +105,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x ",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x ", $time, cyc, crc, result);
$write(" %b",o1);
$write(" %b",o2);
$write(" %b",o3);
@@ -136,8 +136,8 @@ module t (/*AUTOARG*/
$write("\n");
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -149,7 +149,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h2756ea365ec7520e
diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v
index dc94b5aa3..856547a66 100644
--- a/test_regress/t/t_math_real.v
+++ b/test_regress/t/t_math_real.v
@@ -28,7 +28,7 @@ module t (/*AUTOARG*/
reg [95:0] ci96;
reg signed [95:0] cis96;
real r, r2;
- integer cyc=0;
+ integer cyc = 0;
realtime uninit;
initial if (uninit != 0.0) $stop;
@@ -139,7 +139,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
diff --git a/test_regress/t/t_math_real_random.v b/test_regress/t/t_math_real_random.v
index 02c86774f..f17e2ddaf 100644
--- a/test_regress/t/t_math_real_random.v
+++ b/test_regress/t/t_math_real_random.v
@@ -12,7 +12,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -47,10 +47,10 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d in=%x\n",$time, cyc, in);
+ $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_math_real_round.v b/test_regress/t/t_math_real_round.v
index 5c6a56870..50ca98a95 100644
--- a/test_regress/t/t_math_real_round.v
+++ b/test_regress/t/t_math_real_round.v
@@ -15,7 +15,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
real r;
reg [31:0] v32;
diff --git a/test_regress/t/t_math_red.v b/test_regress/t/t_math_red.v
index 10cb292b8..fbd156940 100644
--- a/test_regress/t/t_math_red.v
+++ b/test_regress/t/t_math_red.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [67:0] r;
diff --git a/test_regress/t/t_math_shift_rep.v b/test_regress/t/t_math_shift_rep.v
index cd0011fe1..d7e1ad0ec 100644
--- a/test_regress/t/t_math_shift_rep.v
+++ b/test_regress/t/t_math_shift_rep.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v
index e0b20211c..3a78512b4 100644
--- a/test_regress/t/t_math_shift_sel.v
+++ b/test_regress/t/t_math_shift_sel.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc746017202a24ecc
diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v
index 2d62cef84..554297b44 100644
--- a/test_regress/t/t_math_shortreal.v
+++ b/test_regress/t/t_math_shortreal.v
@@ -18,7 +18,7 @@ module t (/*AUTOARG*/
integer i;
reg [63:0] b;
shortreal r, r2;
- integer cyc=0;
+ integer cyc = 0;
realtime uninit;
initial if (uninit != 0.0) $stop;
@@ -86,7 +86,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v
index fc92d0d35..9bdc5d362 100644
--- a/test_regress/t/t_math_signed.v
+++ b/test_regress/t/t_math_signed.v
@@ -98,7 +98,7 @@ module t (/*AUTOARG*/
copy_signed = ai;
endfunction
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
wire [31:0] ucyc = cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
@@ -181,7 +181,7 @@ module by_width (
wire signed [WIDTH-1:0] i65ext = i65;
// verilator lint_on WIDTH
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
i1 <= cyc[0];
diff --git a/test_regress/t/t_math_signed_wire.v b/test_regress/t/t_math_signed_wire.v
index 0ddd9fa97..0f0d3fc62 100644
--- a/test_regress/t/t_math_signed_wire.v
+++ b/test_regress/t/t_math_signed_wire.v
@@ -20,7 +20,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] result=%x %x\n",$time, au, as);
+ $write("[%0t] result=%x %x\n", $time, au, as);
`endif
if (au != 'h12) $stop;
if (as != 'h02) $stop;
diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v
index f5a78c2f3..e59e1c5d8 100644
--- a/test_regress/t/t_math_swap.v
+++ b/test_regress/t/t_math_swap.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -48,13 +48,13 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration);
+ $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n", $time, cyc, crc, result, test.Iteration);
`endif
cyc <= cyc + 1;
if (cyc < 20 || test.Iteration==4'd15) begin
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
end
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -67,7 +67,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'h8dd70a44972ad809) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_trig.v b/test_regress/t/t_math_trig.v
index a87816e80..61204358c 100644
--- a/test_regress/t/t_math_trig.v
+++ b/test_regress/t/t_math_trig.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
input clk;
real r, r2;
- integer cyc=0;
+ integer cyc = 0;
task check(integer line, real got, real ex);
if (got != ex) begin
@@ -90,7 +90,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
r = $itor(cyc)/10.0 - 5.0; // Crosses 0
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n",$time, cyc, r, sum_ln);
+ $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n", $time, cyc, r, sum_ln);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v
index bf6ab7291..42ba7ff86 100644
--- a/test_regress/t/t_math_vliw.v
+++ b/test_regress/t/t_math_vliw.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [223:0] sum;
@@ -42,11 +42,11 @@ module t (/*AUTOARG*/
sum <= 224'h0;
end
else if (cyc<90) begin
- //$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
+ //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_math_yosys.v b/test_regress/t/t_math_yosys.v
index 9fe06d075..e72ac511d 100644
--- a/test_regress/t/t_math_yosys.v
+++ b/test_regress/t/t_math_yosys.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v
index 8702c4969..d4bdc2425 100644
--- a/test_regress/t/t_mem_fifo.v
+++ b/test_regress/t/t_mem_fifo.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
wire [65:0] outData; // From fifo of fifo.v
@@ -33,9 +33,9 @@ module t (/*AUTOARG*/
.wrEn (wrEn));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
+ //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v
index e1a7574ed..9284d9fba 100644
--- a/test_regress/t/t_mem_file.v
+++ b/test_regress/t/t_mem_file.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -49,10 +49,10 @@ module t (/*AUTOARG*/
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
+ //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n", $time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -65,7 +65,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
- $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v
index 22ca9e223..c9c1077a9 100644
--- a/test_regress/t/t_mem_func.v
+++ b/test_regress/t/t_mem_func.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h58b162c58d6e35ba
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v
index 1c044fc6f..93e35744a 100644
--- a/test_regress/t/t_mem_iforder.v
+++ b/test_regress/t/t_mem_iforder.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [31:0] sum;
@@ -36,9 +36,9 @@ module t (/*AUTOARG*/
.inData (inData[15:0]));
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
+ //$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v
index cee7bcd29..3d09878cc 100644
--- a/test_regress/t/t_mem_multidim.v
+++ b/test_regress/t/t_mem_multidim.v
@@ -18,7 +18,7 @@ module t (/*AUTOARG*/
reg [7:0] memn [2:0][1:3][5:2];
// verilator lint_on BLKANDNBLK
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [71:0] wide;
reg [7:0] narrow;
@@ -62,7 +62,7 @@ module t (/*AUTOARG*/
index0 <= crc[1:0];
index1 <= crc[3:2];
index2 <= crc[6:4];
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
// We never read past bounds, or get unspecific results
// We also never read lowest indexes, as writing outside of range may corrupt them
@@ -88,7 +88,7 @@ module t (/*AUTOARG*/
else if (cyc==91) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide);
+ $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide);
if (crc != 64'h65e3bddcd9bc2750) $stop;
if (narrow != 8'hca) $stop;
if (wide != 72'h4edafed31ba6873f73) $stop;
diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v
index 663df9be3..c031b44ce 100644
--- a/test_regress/t/t_mem_multiwire.v
+++ b/test_regress/t/t_mem_multiwire.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
wire [7:0] arrayNoColon [2][3];
// verilator lint_on LITENDIAN
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
integer i0,i1,i2;
genvar g0,g1,g2;
diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v
index 52a38bf9d..2a90a7462 100644
--- a/test_regress/t/t_mem_packed.v
+++ b/test_regress/t/t_mem_packed.v
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
sum_w <= sum_w + arr_w[cyc-10];
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
+ $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum);
if (sum != 8'h55) $stop;
if (sum != sum_w) $stop;
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v
index 9302f09e1..a2e84d6cf 100644
--- a/test_regress/t/t_mem_shift.v
+++ b/test_regress/t/t_mem_shift.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
integer i;
@@ -34,9 +34,9 @@ module t (/*AUTOARG*/
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
+ //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v
index 2f7118f1f..cca91bb24 100644
--- a/test_regress/t/t_mem_slice_conc_bad.v
+++ b/test_regress/t/t_mem_slice_conc_bad.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
rst <= 1'b0;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v
index 9c241853c..8d4f48303 100644
--- a/test_regress/t/t_mem_twoedge.v
+++ b/test_regress/t/t_mem_twoedge.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -41,16 +41,16 @@ module t (/*AUTOARG*/
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -64,7 +64,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
diff --git a/test_regress/t/t_merge_cond.v b/test_regress/t/t_merge_cond.v
index 2484c11cc..110ebcc43 100644
--- a/test_regress/t/t_merge_cond.v
+++ b/test_regress/t/t_merge_cond.v
@@ -12,13 +12,13 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc= 64'h5aef0c8d_d70a4497;
reg [63:0] prev_crc;
always @ (posedge clk) begin
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
prev_crc <= crc;
if (cyc==99) begin
diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v
index 096843aad..370900e77 100644
--- a/test_regress/t/t_mod_recurse.v
+++ b/test_regress/t/t_mod_recurse.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -31,11 +31,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -47,7 +47,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc5fc632f816568fb
diff --git a/test_regress/t/t_optm_redor.v b/test_regress/t/t_optm_redor.v
index 11df0a68f..b902bcdca 100644
--- a/test_regress/t/t_optm_redor.v
+++ b/test_regress/t/t_optm_redor.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h162c58b1635b8d6e
diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v
index 3613c85c9..6ec373cbe 100644
--- a/test_regress/t/t_order.v
+++ b/test_regress/t/t_order.v
@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
// End of automatics
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
t_order_a a (
.one (8'h1),
@@ -89,7 +89,7 @@ module t (/*AUTOARG*/
end
if (cyc == 8'd3) begin
- $display("%d %d %d %d",m_from_clk_lev1_r,
+ $display("%d %d %d %d", m_from_clk_lev1_r,
n_from_clk_lev2,
o_from_com_levs11,
o_from_comandclk_levs12);
diff --git a/test_regress/t/t_order_2d.v b/test_regress/t/t_order_2d.v
index 84e45021b..32132d1b1 100644
--- a/test_regress/t/t_order_2d.v
+++ b/test_regress/t/t_order_2d.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h765b2e12b25ec97b
diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v
index 859224e98..048f5851b 100644
--- a/test_regress/t/t_order_clkinst.v
+++ b/test_regress/t/t_order_clkinst.v
@@ -28,9 +28,9 @@ module t (/*AUTOARG*/
wire [31:0] c3_count;
comb_loop c3 (.count(c3_count), .start(c3_start));
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
- //$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count);
+ //$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
diff --git a/test_regress/t/t_order_comboclkloop.v b/test_regress/t/t_order_comboclkloop.v
index 373c510bd..a4360e2f1 100644
--- a/test_regress/t/t_order_comboclkloop.v
+++ b/test_regress/t/t_order_comboclkloop.v
@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
- $write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
+ $write(" seq runcount=%0d runner =%0x\n", runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
@@ -42,9 +42,9 @@ module t (/*AUTOARG*/
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
- $write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
+ $write("[%0t] %x counts %0x %0x\n", $time, cyc, runcount, clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v
index c0a32f4d9..8607ccc96 100644
--- a/test_regress/t/t_order_doubleloop.v
+++ b/test_regress/t/t_order_doubleloop.v
@@ -26,7 +26,7 @@ module t (/*AUTOARG*/
reg [31:0] dlyrun; initial dlyrun = 0;
reg [31:0] dlyrunm1;
always @ (posedge clk) begin
- $write("[%0t] cyc %d\n",$time,cyc);
+ $write("[%0t] cyc %d\n", $time,cyc);
cyc <= cyc + 1;
if (cyc==2) begin
// Test # of iters
@@ -74,7 +74,7 @@ module t (/*AUTOARG*/
if (comrun!=0) begin
comrunm1 = comrun - 32'd1;
comcnt = comcnt + 32'd1;
- $write("[%0t] comcnt=%0d\n",$time,comcnt);
+ $write("[%0t] comcnt=%0d\n", $time,comcnt);
end
end
diff --git a/test_regress/t/t_param_array6.v b/test_regress/t/t_param_array6.v
index 34766e731..708935749 100644
--- a/test_regress/t/t_param_array6.v
+++ b/test_regress/t/t_param_array6.v
@@ -49,7 +49,7 @@ module t import test_pkg::*; (clk);
$display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2);
`endif
if (cyc > 10 && cyc < 90) begin
- sum <= {48'h0, temp} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
end
else if (cyc == 99) begin
$displayh(sum);
diff --git a/test_regress/t/t_param_if_blk.v b/test_regress/t/t_param_if_blk.v
index b2a71800d..b3a24bfdf 100644
--- a/test_regress/t/t_param_if_blk.v
+++ b/test_regress/t/t_param_if_blk.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -55,7 +55,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h9d550d82d38926fa
diff --git a/test_regress/t/t_param_sel.v b/test_regress/t/t_param_sel.v
index 3c91fef16..d79ed9d18 100644
--- a/test_regress/t/t_param_sel.v
+++ b/test_regress/t/t_param_sel.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
diff --git a/test_regress/t/t_past.v b/test_regress/t/t_past.v
index 6f5a353b0..250810185 100644
--- a/test_regress/t/t_past.v
+++ b/test_regress/t/t_past.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -30,7 +30,7 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
diff --git a/test_regress/t/t_pgo_profoutofdate_bad.v b/test_regress/t/t_pgo_profoutofdate_bad.v
index cba43da97..43a2b1b8d 100755
--- a/test_regress/t/t_pgo_profoutofdate_bad.v
+++ b/test_regress/t/t_pgo_profoutofdate_bad.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
// Test loop
always @ (posedge clk) begin
diff --git a/test_regress/t/t_prof.v b/test_regress/t/t_prof.v
index ae605781c..ee63a2f6b 100644
--- a/test_regress/t/t_prof.v
+++ b/test_regress/t/t_prof.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
wire [63:0] result;
Test test(/*AUTOINST*/
@@ -25,10 +25,10 @@ module t(/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d result=%x\n",$time, cyc, result);
+ $write("[%0t] cyc==%0d result=%x\n", $time, cyc, result);
`endif
cyc <= cyc + 1;
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
sum <= '0;
@@ -39,7 +39,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
+ $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum);
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hfefad16f06ba6b1f
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_prot_lib.v b/test_regress/t/t_prot_lib.v
index b0195a940..d3dad3679 100644
--- a/test_regress/t/t_prot_lib.v
+++ b/test_regress/t/t_prot_lib.v
@@ -107,7 +107,7 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
$time, x, cyc, accum_in, accum_out, accum_bypass_out);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
accum_in <= accum_in + 5;
`DRIVE(s1)
`DRIVE(s2)
diff --git a/test_regress/t/t_queue.v b/test_regress/t/t_queue.v
index 0d3ded455..3c5db893c 100644
--- a/test_regress/t/t_queue.v
+++ b/test_regress/t/t_queue.v
@@ -15,7 +15,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
integer i;
diff --git a/test_regress/t/t_reloop_cam.v b/test_regress/t/t_reloop_cam.v
index 4333577ec..5c568524f 100644
--- a/test_regress/t/t_reloop_cam.v
+++ b/test_regress/t/t_reloop_cam.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg rst;
@@ -59,11 +59,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -81,7 +81,7 @@ module t (/*AUTOARG*/
inval <= 1'b0;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h5182640870b07199
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v
index 1fc854566..3edc34885 100644
--- a/test_regress/t/t_savable.v
+++ b/test_regress/t/t_savable.v
@@ -30,7 +30,7 @@ module sub (/*AUTOARG*/
input clk;
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
- integer cyc=0;
+ integer cyc = 0;
reg [127:0] save128;
reg [47:0] save48;
@@ -48,7 +48,7 @@ module sub (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d\n",$time, cyc);
+ $write("[%0t] cyc==%0d\n", $time, cyc);
`endif
si = "siimmed";
cyc <= cyc + 1;
diff --git a/test_regress/t/t_select_2d.v b/test_regress/t/t_select_2d.v
index bbe492e52..4de9b5f01 100644
--- a/test_regress/t/t_select_2d.v
+++ b/test_regress/t/t_select_2d.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t(/*AUTOARG*/
else if (cyc < 90) begin
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h1f324087bbba0bfa
diff --git a/test_regress/t/t_select_bad_range2.v b/test_regress/t/t_select_bad_range2.v
index ae1ab47d9..0efb7ce2d 100644
--- a/test_regress/t/t_select_bad_range2.v
+++ b/test_regress/t/t_select_bad_range2.v
@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
- $write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
+ $write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v
index af2861c60..07f38acbf 100644
--- a/test_regress/t/t_select_bound1.v
+++ b/test_regress/t/t_select_bound1.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
+ $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha9d3a7a69d2bea75
diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v
index 681a92457..c414fbfc0 100644
--- a/test_regress/t/t_select_bound2.v
+++ b/test_regress/t/t_select_bound2.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -38,11 +38,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
+ $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e9d3a74e9d3f656
diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v
index b34470849..826d794a9 100644
--- a/test_regress/t/t_select_lhs_oob.v
+++ b/test_regress/t/t_select_lhs_oob.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
clk
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
@@ -57,7 +57,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
+ $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n", $time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
diff --git a/test_regress/t/t_select_lhs_oob2.v b/test_regress/t/t_select_lhs_oob2.v
index 10cff1cf9..81d634caf 100644
--- a/test_regress/t/t_select_lhs_oob2.v
+++ b/test_regress/t/t_select_lhs_oob2.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -43,11 +43,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -59,7 +59,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h421a41d1541ea652
diff --git a/test_regress/t/t_select_little.v b/test_regress/t/t_select_little.v
index 2b7b9e93c..b33d7a137 100644
--- a/test_regress/t/t_select_little.v
+++ b/test_regress/t/t_select_little.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -47,12 +47,12 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -63,7 +63,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_select_negative.v b/test_regress/t/t_select_negative.v
index bd0e66687..e62df8185 100644
--- a/test_regress/t/t_select_negative.v
+++ b/test_regress/t/t_select_negative.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -42,12 +42,12 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21,out22,out23, out31,out32,out33);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -58,7 +58,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v
index 247f166f8..11ed4a9bc 100644
--- a/test_regress/t/t_select_plus.v
+++ b/test_regress/t/t_select_plus.v
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/
reg [3:0] nibblep;
reg [3:0] nibblem;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
always @* begin
nibblep = from[bitn +: 4];
@@ -28,7 +28,7 @@ module t (/*AUTOARG*/
end
always @ (posedge clk) begin
- //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to);
+ //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end
diff --git a/test_regress/t/t_select_plus_mul_pow2.v b/test_regress/t/t_select_plus_mul_pow2.v
index d533b88ab..6126383a5 100644
--- a/test_regress/t/t_select_plus_mul_pow2.v
+++ b/test_regress/t/t_select_plus_mul_pow2.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
reg [63:0] from = 64'h0706050403020100;
reg [7:0] to;
reg [2:0] bitn;
- reg [7:0] cyc; initial cyc=0;
+ reg [7:0] cyc; initial cyc = 0;
always @* begin
to = from[bitn * 8 +: 8];
diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v
index 58249e4ee..7a5ee64f0 100644
--- a/test_regress/t/t_select_plusloop.v
+++ b/test_regress/t/t_select_plusloop.v
@@ -15,12 +15,12 @@ module t (/*AUTOARG*/
reg [63:0] quad;
reg [127:0] wide;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [6:0] index;
always @ (posedge clk) begin
- //$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow);
+ //$write("[%0t] cyc==%0d crc=%b n=%x\n", $time, cyc, crc, narrow);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
@@ -54,7 +54,7 @@ module t (/*AUTOARG*/
wide[81] <=1'b1;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide);
+ $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide);
if (crc != 8'b01111001) $stop;
if (narrow != 32'h001661c7) $stop;
if (quad != 64'h16d49b6f64266039) $stop;
diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v
index b43330e11..40a57b989 100644
--- a/test_regress/t/t_select_runtime_range.v
+++ b/test_regress/t/t_select_runtime_range.v
@@ -53,10 +53,10 @@ module t (clk);
end
if (cyc==5) begin
read = mi[index];
- $display("-Illegal read value: %x",read);
+ $display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
- $display("-Illegal read value: %x",read);
+ $display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
@@ -64,7 +64,7 @@ module t (clk);
end
if (cyc==7) begin
read = mi[indexi];
- $display("-Illegal read value: %x",read);
+ $display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v
index c317d5f9e..ee3db8562 100644
--- a/test_regress/t/t_split_var_0.v
+++ b/test_regress/t/t_split_var_0.v
@@ -289,7 +289,7 @@ module t_array_rev(clk); // from t_array_rev.v
input clk;
- integer cyc=0;
+ integer cyc = 0;
// verilator lint_off LITENDIAN
logic arrd [0:1] /*verilator split_var*/ = '{ 1'b1, 1'b0 };
// verilator lint_on LITENDIAN
diff --git a/test_regress/t/t_split_var_3_wreal.v b/test_regress/t/t_split_var_3_wreal.v
index 068fe0c7b..46cca2e2a 100644
--- a/test_regress/t/t_split_var_3_wreal.v
+++ b/test_regress/t/t_split_var_3_wreal.v
@@ -13,7 +13,7 @@ module t (/*autoarg*/
input clk;
- integer cyc=0;
+ integer cyc = 0;
real vin[0:1] /*verilator split_var*/;
wreal vout[0:1] /*verilator split_var*/;
diff --git a/test_regress/t/t_split_var_4.v b/test_regress/t/t_split_var_4.v
index f8557f479..7b8a475bc 100644
--- a/test_regress/t/t_split_var_4.v
+++ b/test_regress/t/t_split_var_4.v
@@ -17,7 +17,7 @@ module t(/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -43,19 +43,19 @@ module t(/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$display("o %b", o0);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc == 99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb58b16c592557b30
diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v
index 65d07ffe8..0fadf93ae 100644
--- a/test_regress/t/t_stream2.v
+++ b/test_regress/t/t_stream2.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
@@ -40,8 +40,8 @@ module t (/*AUTOARG*/
$time, cyc, crc, result, amt, left, right);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0da01049b480c38a
diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v
index 76e40a5fc..24b740bf3 100644
--- a/test_regress/t/t_stream3.v
+++ b/test_regress/t/t_stream3.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
@@ -34,7 +34,7 @@ module t (/*AUTOARG*/
$time, cyc, crc);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -46,7 +46,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
diff --git a/test_regress/t/t_string.v b/test_regress/t/t_string.v
index 758d5744e..9e5327f37 100644
--- a/test_regress/t/t_string.v
+++ b/test_regress/t/t_string.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [1*8:1] vstr1;
reg [2*8:1] vstr2;
diff --git a/test_regress/t/t_string_type_methods.v b/test_regress/t/t_string_type_methods.v
index 85e410d71..db9597dbe 100644
--- a/test_regress/t/t_string_type_methods.v
+++ b/test_regress/t/t_string_type_methods.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
string s;
- integer cyc=0;
+ integer cyc = 0;
// Check constification
initial begin
diff --git a/test_regress/t/t_struct_port.v b/test_regress/t/t_struct_port.v
index 58cf5beeb..45a75b527 100644
--- a/test_regress/t/t_struct_port.v
+++ b/test_regress/t/t_struct_port.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -41,11 +41,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
+ $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n", $time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -57,7 +57,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
diff --git a/test_regress/t/t_struct_portsel.v b/test_regress/t/t_struct_portsel.v
index 3146a3eab..18f8133d0 100644
--- a/test_regress/t/t_struct_portsel.v
+++ b/test_regress/t/t_struct_portsel.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -34,11 +34,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdb7bc61592f31b99
diff --git a/test_regress/t/t_struct_unaligned.v b/test_regress/t/t_struct_unaligned.v
index 8fdb06cb1..81c64f001 100644
--- a/test_regress/t/t_struct_unaligned.v
+++ b/test_regress/t/t_struct_unaligned.v
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/
logic [130:0] data;
} foo[1];
- integer cyc=0;
+ integer cyc = 0;
// Test loop
always @ (posedge clk) begin
diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v
index 0a05a6cdb..81f0b1422 100644
--- a/test_regress/t/t_sys_time.v
+++ b/test_regress/t/t_sys_time.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] time64;
diff --git a/test_regress/t/t_table_fsm.v b/test_regress/t/t_table_fsm.v
index f4d574288..4eab60786 100644
--- a/test_regress/t/t_table_fsm.v
+++ b/test_regress/t/t_table_fsm.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
@@ -36,11 +36,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending);
+ $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
diff --git a/test_regress/t/t_time_sc.v b/test_regress/t/t_time_sc.v
index 50f48f359..fa799a00d 100644
--- a/test_regress/t/t_time_sc.v
+++ b/test_regress/t/t_time_sc.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
time texpect = `TEST_EXPECT;
diff --git a/test_regress/t/t_time_stamp64.v b/test_regress/t/t_time_stamp64.v
index 2c965a83c..cd6c0aa27 100644
--- a/test_regress/t/t_time_stamp64.v
+++ b/test_regress/t/t_time_stamp64.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
diff --git a/test_regress/t/t_trace_array.v b/test_regress/t/t_trace_array.v
index 9622f78ff..e98e1de1a 100644
--- a/test_regress/t/t_trace_array.v
+++ b/test_regress/t/t_trace_array.v
@@ -6,7 +6,7 @@
module t (clk);
input clk;
- integer cyc=0;
+ integer cyc = 0;
// Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk
diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v
index baae75453..9572e92dc 100644
--- a/test_regress/t/t_trace_complex.v
+++ b/test_regress/t/t_trace_complex.v
@@ -8,7 +8,7 @@ bit global_bit;
module t (clk);
input clk;
- integer cyc=0;
+ integer cyc = 0;
typedef struct packed {
bit b1;
diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v
index 7601f94f2..e79ba3d6d 100644
--- a/test_regress/t/t_tri_array.v
+++ b/test_regress/t/t_tri_array.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -33,12 +33,12 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {60'h0, pad[3], pad[2], pad[1], pad[0]}
- ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -50,7 +50,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he09fe6f2dfd7a302
diff --git a/test_regress/t/t_tri_array_bufif.v b/test_regress/t/t_tri_array_bufif.v
index 44489b7f6..1d0cb1d17 100644
--- a/test_regress/t/t_tri_array_bufif.v
+++ b/test_regress/t/t_tri_array_bufif.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -46,11 +46,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
+ $write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n", $time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -63,7 +63,7 @@ module t (/*AUTOARG*/
if (drv2 != drv) $stop;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hd95d216c5a2945d0
diff --git a/test_regress/t/t_tri_eqcase.v b/test_regress/t/t_tri_eqcase.v
index a922a4b94..7644426c9 100644
--- a/test_regress/t/t_tri_eqcase.v
+++ b/test_regress/t/t_tri_eqcase.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -43,11 +43,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
+ $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n", $time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -59,7 +59,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
diff --git a/test_regress/t/t_tri_pull01.v b/test_regress/t/t_tri_pull01.v
index 2d1248a9b..54d4b41e0 100644
--- a/test_regress/t/t_tri_pull01.v
+++ b/test_regress/t/t_tri_pull01.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -40,11 +40,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -56,7 +56,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h04f91df71371e950
diff --git a/test_regress/t/t_tri_unconn.v b/test_regress/t/t_tri_unconn.v
index 368c2638f..2cdf59228 100644
--- a/test_regress/t/t_tri_unconn.v
+++ b/test_regress/t/t_tri_unconn.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
wire one = '1;
wire z0 = 'z;
diff --git a/test_regress/t/t_typedef_param.v b/test_regress/t/t_typedef_param.v
index c9c98202f..8375d7a90 100644
--- a/test_regress/t/t_typedef_param.v
+++ b/test_regress/t/t_typedef_param.v
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -46,11 +46,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -62,7 +62,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
diff --git a/test_regress/t/t_typedef_port.v b/test_regress/t/t_typedef_port.v
index 44d24d05d..2f0370710 100644
--- a/test_regress/t/t_typedef_port.v
+++ b/test_regress/t/t_typedef_port.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
typedef reg [2:0] three_t;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -47,11 +47,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -63,7 +63,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
diff --git a/test_regress/t/t_typedef_signed.v b/test_regress/t/t_typedef_signed.v
index 0f7bf55ee..1f3d78b67 100644
--- a/test_regress/t/t_typedef_signed.v
+++ b/test_regress/t/t_typedef_signed.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -39,11 +39,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -53,7 +53,7 @@ module t (/*AUTOARG*/
sum <= 64'h0;
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7211d24a17b25ec9
diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v
index a40afa70e..26eb1104d 100644
--- a/test_regress/t/t_udp.v
+++ b/test_regress/t/t_udp.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -69,11 +69,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -85,7 +85,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
// Note not all simulators agree about the latch result. Maybe have a race?
diff --git a/test_regress/t/t_udp_noname.v b/test_regress/t/t_udp_noname.v
index 258f6f42e..484dbb03a 100644
--- a/test_regress/t/t_udp_noname.v
+++ b/test_regress/t/t_udp_noname.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
wire o;
udp (o, a);
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
// Test loop
always @ (posedge clk) begin
diff --git a/test_regress/t/t_unopt_array.v b/test_regress/t/t_unopt_array.v
index 1158c8bb4..1ca4db785 100644
--- a/test_regress/t/t_unopt_array.v
+++ b/test_regress/t/t_unopt_array.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -35,11 +35,11 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+ $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
- sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h458c2de282e30f8b
diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v
index c4d7e6d14..6620e7459 100644
--- a/test_regress/t/t_unopt_combo.v
+++ b/test_regress/t/t_unopt_combo.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
@@ -35,12 +35,12 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
+ $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n", $time, cyc, crc, sum, b, d);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {b, d}
- ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+ ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
@@ -52,7 +52,7 @@ module t (/*AUTOARG*/
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
- $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v
index 5be7038bf..e565137b7 100644
--- a/test_regress/t/t_unroll_signed.v
+++ b/test_regress/t/t_unroll_signed.v
@@ -31,7 +31,7 @@ module t (/*AUTOARG*/
reg [31:0] dly_to_ensure_was_unrolled [1:0];
reg [2:0] i3;
- integer cyc; initial cyc=0;
+ integer cyc; initial cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
case (cyc)
diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v
index d2c453b9b..6fe807df3 100644
--- a/test_regress/t/t_vams_wreal.v
+++ b/test_regress/t/t_vams_wreal.v
@@ -16,7 +16,7 @@ module t (/*autoarg*/
input [15:0] in;
wreal aout;
- integer cyc=0;
+ integer cyc = 0;
real vin;
wreal vpass;
@@ -59,7 +59,7 @@ module t (/*autoarg*/
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n",$time, cyc, out, vin, gnd, within_range.in_int);
+ $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int);
`endif
if (cyc==0) begin
// Setup
diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v
index 4713eea8f..dabaa0cef 100644
--- a/test_regress/t/t_var_assign_landr.v
+++ b/test_regress/t/t_var_assign_landr.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
reg [63:0] crc;
reg [255:0] sum;
@@ -33,10 +33,10 @@ module t (/*AUTOARG*/
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d crc=%x result=%x %x\n",$time, cyc, crc, o1, o2);
+ $write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2);
`endif
cyc <= cyc + 1;
- crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
@@ -49,7 +49,7 @@ module t (/*AUTOARG*/
else if (cyc<90) begin
end
else if (cyc==99) begin
- $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a
diff --git a/test_regress/t/t_var_in_assign.v b/test_regress/t/t_var_in_assign.v
index 263775599..aa41a3d03 100644
--- a/test_regress/t/t_var_in_assign.v
+++ b/test_regress/t/t_var_in_assign.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
);
input clk;
- integer cyc=0;
+ integer cyc = 0;
integer v;
reg i;
@@ -24,7 +24,7 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
- $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
+ $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
diff --git a/test_regress/t/t_verilated_debug.v b/test_regress/t/t_verilated_debug.v
index 9cd229c4f..3f4e000eb 100644
--- a/test_regress/t/t_verilated_debug.v
+++ b/test_regress/t/t_verilated_debug.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
initial begin
// internal code coverage for _vl_debug_print_w
wide = {32'haa, 32'hbb, 32'hcc};
- $c("_vl_debug_print_w(",$bits(wide),",",wide,");");
+ $c("_vl_debug_print_w(", $bits(wide), ", ", wide, ");");
end
// Test loop
diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out
index 791baf602..bbe26868f 100644
--- a/test_regress/t/t_xml_debugcheck.out
+++ b/test_regress/t/t_xml_debugcheck.out
@@ -842,13 +842,13 @@
-
+
-
-
-
+
+
+
@@ -1411,7 +1411,7 @@
-
+
@@ -1544,7 +1544,7 @@
-
+