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Tests: Remove CRs.

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This commit is contained in:
Wilson Snyder 2019-06-04 20:37:16 -04:00
parent 4e115d4b69
commit 38ad8727af
3 changed files with 47 additions and 47 deletions
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38
test_regress/t/t_sv_cpu_code/pad_gnd.sv
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@ -1,19 +1,19 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_GND - Ground Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_gnd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b0;
endmodule // pad_gnd
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_GND - Ground Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_gnd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b0;
endmodule // pad_gnd

38
test_regress/t/t_sv_cpu_code/pad_vdd.sv
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@ -1,19 +1,19 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_VDD - VDD Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_vdd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b1;
endmodule // pad_vdd
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_VDD - VDD Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_vdd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b1;
endmodule // pad_vdd

18
test_regress/t/t_sv_cpu_code/timescale.sv
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@ -1,9 +1,9 @@
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
// **** Set simulation time scale ****
`timescale 1ns/1ps
// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
// **** Set simulation time scale ****
`timescale 1ns/1ps