From 38ad8727af9b7cd12aa1306b34ff45920f90b95c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 4 Jun 2019 20:37:16 -0400
Subject: [PATCH] Tests: Remove CRs.

---
 test_regress/t/t_sv_cpu_code/pad_gnd.sv   | 38 +++++++++++------------
 test_regress/t/t_sv_cpu_code/pad_vdd.sv   | 38 +++++++++++------------
 test_regress/t/t_sv_cpu_code/timescale.sv | 18 +++++------
 3 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/test_regress/t/t_sv_cpu_code/pad_gnd.sv b/test_regress/t/t_sv_cpu_code/pad_gnd.sv
index b73e755ba..c9481edea 100644
--- a/test_regress/t/t_sv_cpu_code/pad_gnd.sv
+++ b/test_regress/t/t_sv_cpu_code/pad_gnd.sv
@@ -1,19 +1,19 @@
-// DESCRIPTION: Verilator: Large test for SystemVerilog
-
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2012.
-
-// Contributed by M W Lund, Atmel Corporation.
-
-//*****************************************************************************
-// PAD_GND - Ground Supply Pad (Dummy!!!!)
-//*****************************************************************************
-
-module pad_gnd
-#( parameter ID = 0 )
-  (
-   inout wire pad
-   );
-
-  assign pad = 1'b0;
-endmodule // pad_gnd
+// DESCRIPTION: Verilator: Large test for SystemVerilog
+
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012.
+
+// Contributed by M W Lund, Atmel Corporation.
+
+//*****************************************************************************
+// PAD_GND - Ground Supply Pad (Dummy!!!!)
+//*****************************************************************************
+
+module pad_gnd
+#( parameter ID = 0 )
+  (
+   inout wire pad
+   );
+
+  assign pad = 1'b0;
+endmodule // pad_gnd
diff --git a/test_regress/t/t_sv_cpu_code/pad_vdd.sv b/test_regress/t/t_sv_cpu_code/pad_vdd.sv
index ed26fb217..0096dbc1e 100644
--- a/test_regress/t/t_sv_cpu_code/pad_vdd.sv
+++ b/test_regress/t/t_sv_cpu_code/pad_vdd.sv
@@ -1,19 +1,19 @@
-// DESCRIPTION: Verilator: Large test for SystemVerilog
-
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2012.
-
-// Contributed by M W Lund, Atmel Corporation.
-
-//*****************************************************************************
-// PAD_VDD - VDD Supply Pad (Dummy!!!!)
-//*****************************************************************************
-
-module pad_vdd
-#( parameter ID = 0 )
-  (
-   inout wire pad
-   );
-
-  assign pad = 1'b1;
-endmodule // pad_vdd
+// DESCRIPTION: Verilator: Large test for SystemVerilog
+
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012.
+
+// Contributed by M W Lund, Atmel Corporation.
+
+//*****************************************************************************
+// PAD_VDD - VDD Supply Pad (Dummy!!!!)
+//*****************************************************************************
+
+module pad_vdd
+#( parameter ID = 0 )
+  (
+   inout wire pad
+   );
+
+  assign pad = 1'b1;
+endmodule // pad_vdd
diff --git a/test_regress/t/t_sv_cpu_code/timescale.sv b/test_regress/t/t_sv_cpu_code/timescale.sv
index 2a5aab4bc..1bb501097 100644
--- a/test_regress/t/t_sv_cpu_code/timescale.sv
+++ b/test_regress/t/t_sv_cpu_code/timescale.sv
@@ -1,9 +1,9 @@
-// DESCRIPTION: Verilator: Large test for SystemVerilog
-
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2012.
-
-// Contributed by M W Lund, Atmel Corporation.
-
-// **** Set simulation time scale ****
-`timescale 1ns/1ps
+// DESCRIPTION: Verilator: Large test for SystemVerilog
+
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012.
+
+// Contributed by M W Lund, Atmel Corporation.
+
+// **** Set simulation time scale ****
+`timescale 1ns/1ps